Voltage transfer circuit

A selectable output voltage transfer circuit comprising:

• a first voltage input;
• a second voltage input;
• a selection signal input;
• a voltage output;
• an input-transfer circuit for receiving a first input voltage from the first voltage input;
• a standby circuit for receiving a second input voltage from the second voltage input;
• a switching circuit for receiving a selection signal from the selection signal input and for controlling, according to the selection signal, the standby circuit and the input-transfer circuit to generate an output voltage that is based on one of the first and second input voltages;
• and
• an output voltage feedback circuit connected to the voltage output for minimizing leakage current by adjusting a voltage bias across a component of at least one of the standby circuit and the input-transfer circuit.

A transfer circuit for supplying an output voltage equivalent to an input voltage when in an active mode and equivalent to a standby voltage when in a standby mode, the circuit comprising:

• a standby circuit;
• an input-transfer circuit;
• and
• a switching circuit for controlling the standby circuit to supply the output voltage equivalent to the standby voltage for said standby mode, and for controlling, by supplying an equivalent of the output voltage, the input-transfer circuit to supply the output voltage equivalent to the input voltage for said active mode.

A transfer circuit comprising:

• an input line for receiving an input voltage;
• an output line for supplying an output voltage;
• a control line for receiving an enable signal;
• a CMOS device for supplying a switching voltage;
• a feedback line for supplying a feedback of said output voltage to said CMOS device,
• wherein said CMOS device is connected to said control line for receiving said enable signal and for controlling said switching voltage based on said enable signal to have one of a first voltage level and a second voltage level, said second voltage level being equivalent to said feedback of said output voltage;
• an NMOS transistor having a gate connected to said CMOS device for receiving said switching voltage and having a drain connected to said output line for supplying an equivalent of a standby voltage to said output line when said switching voltage is at said first voltage level;
• and
• a first PMOS transistor having a source connected to said input line and a drain connected to said output line for supplying an equivalent of said input voltage to said output line when said switching voltage is at said second voltage level.

A circuit comprising:

• an input line, an output line, a control line, a signal ground line, and a source voltage line;
• a first NMOS transistor having a source connected to the signal ground line, a drain connected to the output line, and a gate;
• a second NMOS transistor having a source connected to the output line, a drain connected to the gate of the first NMOS transistor, and a gate connected to the control line;
• a first PMOS transistor having a source connected to the input line, a drain connected to the output line, and a gate;
• a second PMOS transistor having a source and a drain both connected to the drain of the second NMOS transistor, and a gate connected to the gate of the first PMOS transistor;
• a third PMOS transistor having a source connected to the output line, a drain connected to the gate of the first PMOS transistor, and a gate connected to the input line;
• and
• a fourth PMOS transistor having a source connected to the source voltage line, a drain connected to the drain of the second NMOS transistor, and a gate connected to the control line.