US 2006/0232319 A1Published application

Level shifter circuit

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsMitsuaki Osame, Hiromi Yanai

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Abstract

A low-power consumption level shifter circuit is provided by preventing a through current which is generated when a level of a signal is changed. In order to prevent a through current which flows when a level of a signal of the input is changed, the p-channel TFTs are controlled so that the p-channel TFTs and the n-channel TFT or the p-channel TFTs and the n-channel TFT are not turned on at once. A high level signal is inputted to the gate of the n-channel TFT, and at the moment when the n-channel TFT is turned on, the p-channel TFT is turned off. Similarly, at the moment when the n-channel TFT is turned on, the p-channel TFT is turned off. The p-channel TFTs and the n-channel TFT, or the p-channel TFTs and the n-channel TFT are not turned on at once, thereby a path in which the through current flows is cut off.

Claims12

Dependent claims

A level shifter circuit comprising a first power source;

a second power source imparting a potential lower than that of the first power source;
a first p-channel transistor, a second p-channel transistor;
a third p-channel transistor;
a fourth p-channel transistor;
a first n-channel transistor;
a second n-channel transistor;
a first inputting unit for inputting a signal to a gate of the second p-channel transistor;
and a second inputting unit for inputting a signal to a gate of the fourth p-channel transistor;
wherein each of the first inputting unit and the second inputting unit outputs a signal which is different from that inputted to a gate of the first n-channel transistor or the second n-channel transistor,
wherein a source and a drain of the first p-channel transistor are connected to the first power source and a source of the second p-channel transistor respectively,
wherein a drain of the second p-channel transistor is connected to a gate of the third p-channel transistor and a drain of the first n-channel transistor,
wherein a source of the first n-channel transistor is connected to the second power source,
wherein a source and a drain of the third p-channel transistor are connected to the first power source and a source of the fourth p-channel transistor respectively,
wherein a drain of the fourth p-channel transistor is connected to a gate of the first p-channel transistor and a drain of the second n-channel transistor, and
wherein a source of the second n-channel transistor is connected to the second power source.

12 more elements

A level shifter circuit comprising a first power source;

a second power source imparting a potential lower than that of the first power source;
a third power source;
a first p-channel transistor;
a second p-channel transistor;
a third p-channel transistor;
a fourth p-channel transistor;
a first n-channel transistor, a second n-channel transistor;
a first inputting unit for inputting a signal to a gate of the second p-channel transistor;
and a second inputting unit for inputting a signal to a gate of the fourth p-channel transistor,
wherein each of the first inputting unit and the second inputting unit outputs a signal which is different from that inputted to a gate of the first n-channel transistor or the second n-channel transistor,
wherein a source and a drain of the first p-channel transistor are connected to the first power source and a source of the second p-channel transistor respectively,
wherein a drain of the second p-channel transistor is connected to a gate of the third p-channel transistor and a drain of the first n-channel transistor,
wherein a source of the first n-channel transistor is connected to the second power source,
wherein a source and a drain of the third p-channel transistor are connected to the first power source and a source of the fourth p-channel transistor respectively,
wherein a drain of the fourth p-channel transistor is connected to a gate of the first p-channel transistor and a drain of the second n-channel transistor,
wherein a source of the second n-channel transistor is connected to the second power source, wherein the first inputting unit includes a fifth p-channel transistor, a third n-channel transistor, and a fourth n-channel transistor,
wherein a source of the fifth p-channel transistor is connected to the first power source and a drain of the same is connected to the gate of the first n-channel transistor through the third n-channel transistor and the fourth n-channel transistor that are connected in series,
wherein a gate of the fourth n-channel transistor is connected to the third power source,
wherein a drain of the fifth p-channel transistor is an output of the first inputting unit,
wherein the second inputting unit includes a sixth p-channel transistor, a fifth n-channel transistor, and a sixth n-channel transistor,
wherein a source of the sixth p-channel transistor is connected to the first power source and a drain of the same is connected to the gate of the second n-channel transistor through the fifth n-channel transistor and the sixth n-channel transistor that are connected in series,
wherein a gate of the sixth n-channel transistor is connected to the third power source,
wherein a drain of the sixth p-channel transistor is an output of the second inputting unit, and
wherein the same control signal is inputted to gates of the fifth p-channel transistor, the third n-channel transistor, the sixth p-channel transistor, and the fifth n-channel transistor.

21 more elements

Dependencies are inferred from the claim text.