System and method for on/off-chip characterization of pulse-width limiter outputs

A system, comprising:

• a first pulse-width limiter configured to receive a known clock signal and to limit a pulse width of received known clock signals to generate a first intermediate signal;
• a first delay circuit coupled to the first pulse-width limiter and configured to receive the first intermediate signal and to delay the first intermediate signal to generate a first delayed signal;
• a first inverter coupled to the first pulse-width limiter and configured to receive the first intermediate signal and to invert the first intermediate signal to generate a first inverted signal;
• a second pulse-width limiter coupled to the first inverter and configured to receive the first inverted signal and to limit a pulse width of the first inverted signal to generate a second intermediate signal;
• a second delay circuit coupled to the second pulse-width limiter and configured to receive the second intermediate signal and to delay the second intermediate signal to generate a second delayed signal;
• and
• an OR gate coupled to the first delay circuit and the second delay circuit and configured to receive the first delayed signal and the second delayed signal, and to perform a logic OR operation on the received first delayed signal and second delayed signal to generate a clock out signal.

A processor for characterization of pulse-width limiter outputs, the processor including a computer program comprising:

• computer program code for receiving a known clock signal;
• computer program code for limiting a pulse width of the received known clock signal through a first pulse-width limiter to generate a first intermediate signal;
• computer program code for delaying the first intermediate signal by a known amount to generate a first delayed signal;
• computer program code for inverting the first intermediate signal to generate a first inverted signal;
• computer program code for limiting a pulse width of the first inverted signal through a second pulse-width limiter to generate a second intermediate signal;
• computer program code for delaying the second intermediate signal by a known amount to generate a second delayed signal;
• and
• computer program code for performing a logic OR operation on the first delayed signal and the second delayed signal to generate a clock out signal.