Logic gate with reduced sub-threshold leak current
AssigneeElpida Memory, Inc.
InventorKyoichi Nagata
Life of this patent
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Abstract
The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor.
Claims12
A logic gate comprising:
- a first transistor for receiving a first voltage at its source, receiving a first input signal at its gate, and supplying a first output signal from its drain;
- a second transistor for receiving at its source a second voltage that is lower than said first voltage, receiving a second input signal at its gate, and supplying a second output signal from its drain;
- and
- a connection-switching unit that is connected between the drains of said first transistor and said second transistor for connecting or cutting off said first transistor and said second transistor.
Dependencies are inferred from the claim text.