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US 2006/0232303 A1Published application
Sense amplifier for flash memory device
AssigneeAtmel Corporation
InventorsKris Li, Jason Guo, Edward Hui
Life of this patent
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Abstract
A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further configured to couple an equalization potential to the first and second power supply nodes when the latch is operating in an equalization mode.
Claims16
A sense amplifier circuit comprising:
- a first inverter and a second inverter, the first inverter and second inverter cross-coupled to produce a latch, the latch having a first signal node and a second signal node, the second signal node configured to produce a logical complement of the first signal node when the sense amplifier is operating in a read-out mode;
- a first latch supply node and a second latch supply node, the first latch supply node configured to couple a first power supply potential to the latch when the sense amplifier is operating in the read-out mode and the second latch supply node configured to couple a second power supply potential to the latch when the sense amplifier is operating in the read-out mode, the first latch supply node and the second latch supply node further configured to couple an equalization potential to the latch when the sense amplifier is operating in an equalization mode, the first latch supply node and the second latch supply node further configured to float the first latch supply node and the second latch supply node when the sense amplifier is operating in a sense mode;
- an equalization node configured to couple the equalization potential to the first signal node and the second signal node when the sense amplifier is operating in the equalization mode;
- a first bitline transistor coupled to the first signal node and a second bitline transistor coupled to the second signal node, the first bitline transistor configured to receive a signal from a first memory cell, the second bitline transistor configured to receive one of a signal from a second memory cell and a reference signal;
- and
- a first read-out node and a second readout node, the first read-out node and second read-out node configured to couple one of the first signal node and the second signal node to a sense amplifier output when the sense amplifier is operating in the read-out mode.
3 more elements
A method for controlling power to a latch circuit within a sense amplifier, the latch circuit having a first latch supply node and a second latch supply node, the method comprising:
- coupling the first latch supply node and the second latch supply node to an equalization potential during an equalization mode;
- floating the first latch supply node and the second latch supply node during a sense mode such that the latch uses substantially no power during the sense mode;
- and
- coupling the first latch supply node to a first power supply potential and the second latch supply node to a second power supply potential during a read-out mode.
1 more element
A method of equalizing a sense amplifier latch circuit, the latch circuit having a first latch supply node, a second latch supply node, a first signal node, and a second signal node, the method comprising:
- producing an equalization potential approximately equal to a logic threshold of the latch circuit;
- coupling the equalization potential to the first latch supply node and the second latch supply node during an equalization mode;
- coupling the equalization potential to the first signal node and the second signal node during the equalization mode;
- and
- maintaining the equalization potential on the first latch supply node, the second latch supply node, the first signal node, and the second signal node for a time sufficient to stabilize the nodes.
2 more elements
A sense amplifier circuit comprising:
- a latching means having a first signal node, a second signal node, a first latch power supply node and a second latch power supply node;
- an equalization means for coupling an equalization potential to the first signal node, the second signal node, the first latch power supply node, and the second latch power supply node when the sense amplifier circuit is operating in an equalization mode;
- a sense means for floating the first latch power supply node and the second latch power supply node during a sense mode, the sense means further coupling the first signal node to a first bitline signal, and to couple the second signal node to one of a second bitline signal, a complement of the first bitline signal, and a reference signal during the sense mode;
- a power supply means for coupling a first power supply potential to the first latch power supply node and a second power supply potential to the second latch power supply node when the sense amplifier circuit is operating in a read-out mode;
- and
- a readout means for outputting an output signal coupled to one of the first signal node and the second signal node during the read-out mode.
3 more elements
A method of coupling a memory bitline to a sense amplifier having a signal line, the method comprising:
- in a FLASH memory sense amplifier having a cross-coupled latch, coupling the signal line to the memory bitline using a high voltage NMOS transistor, the high voltage NMOS transistor being capable of switching and withstanding a memory bitline potential substantially exceeding a voltage range defined by a first power supply potential and a second power supply potential coupled to the sense amplifier;
- regulating a programming operation utilizing the memory bitline and regulating a sensing mode of the sense amplifier so as to ensure that the programming operation and the sensing mode are non-coincident;
- biasing the high voltage NMOS transistor into a first condition during the programming operation utilizing the bitline;
- and
- biasing the high voltage NMOS transistor into a second condition when the sense amplifier is operating in the sensing mode.
2 more elements
A sense amplifier circuit comprising:
- a cross-coupled latch having a first signal point and a second signal point, the second signal point configured to produce the logical complement of the first signal point when the sense amplifier is operating in a read-out mode;
- a first high voltage NMOS transistor coupled to the first signal point, and a second high voltage NMOS transistor coupled to the second signal point, the first high voltage NMOS transistor further coupled to a first FLASH memory cell, the second high voltage NMOS transistor coupled to one of a second FLASH memory cell and a reference signal;
- and
- a first read-out transistor and a second read-out transistor, the first read-out transistor and the second read-out transistor configured to couple one of the first signal point and the second signal point to a sense amplifier output when the sense amplifier is operating in the read-out mode.
1 more element
Dependencies are inferred from the claim text.