# US 2006/0232300 A1 · Semiconductor integrated circuit device manufacturing method

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- Number: US 2006/0232300 A1
- Document ID: US20060232300A1
- Status: Published application
- Kind: A1
- Application number: 11/402,862
- Filed: 2006-04-13
- Published: 2006-10-19
- Earliest claimed: 2005-04-15
- Assignees: NEC Electronics Corporation
- Inventors: Makoto Oyamada
- Web page: https://patentgrep.com/patent/US20060232300A1

## CPC

- G03F 7/70358: {Scanning exposure, i.e. relative movement of patterned beam and workpiece during imaging}
- G03F 7/70425: {Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM11 to CCM22 to be subject to substrate bias control formed in a core region 10 is performed using a step-and-scan type projection exposure apparatus, scanning is performed in the same direction as a longitudinal direction of the respective CMOS circuit module regions CCM11 to CCM22. In this device, a gate insulating film is formed on the substrate, a gate electrode material film is formed on the gate insulating film, and a photoresist film is formed on the gate electrode material film.

## Claims

### Claim 1

A semiconductor integrated circuit device manufacturing method comprising the steps of:
(a) providing a wafer substrate including a semiconductor integrated circuit device having a plurality of CMOS circuit module regions formed in a core region thereof, said CMOS circuit module regions being subject to substrate bias control, said semiconductor integrated circuit device being configured to include a gate insulating film formed on said substrate, a gate electrode material film formed on said gate insulating film, and a photoresist film formed on said gate electrode material film; and
(b) exposing said water substrate using a step-and-scan type projection exposure apparatus;
wherein upon said exposing, scanning is performed in a same direction as a longitudinal direction of each of said CMOS circuit module regions in said core region.

### Claim 2 (depends on 1)

The semiconductor integrated circuit device according to claim 1, wherein a gate pattern associated with circuit functional modules of said CMOS circuit module regions in said core region is formed in a photomask used at a time of the exposure by said step-and-scan type projection exposure apparatus, and a longitudinal direction of said gate pattern is arranged in a same direction as a scan direction of said step-and-scan type projection exposure apparatus.

### Claim 3

A semiconductor integrated circuit device manufacturing method comprising the steps of:
(a) providing a wafer substrate including a semiconductor integrated circuit device having a plurality of CMOS circuit module regions formed in an input/output region thereof, said CMOS circuit module regions being subject to substrate bias control, said semiconductor integrated circuit device being configured to include a gate insulating film formed on said substrate, a gate electrode material film formed on said gate insulating film, and a photoresist film formed on said gate electrode material film; and
(b) exposing said water substrate using a step-and-scan type projection exposure apparatus,
wherein upon said exposing, scanning is performed in a same direction as a direction of boundaries between said CMOS circuit module regions being adjacent to one another in said input/output region.

### Claim 4 (depends on 3)

The semiconductor integrated circuit device manufacturing method according to claim 3, wherein a gate pattern associated with circuit functional modules of said CMOS circuit module regions in said input/output region is formed in a photomask used at a time of the exposure by said step-and-scan type projection exposure apparatus, and a longitudinal direction of said gate pattern is arranged in a same direction as a scan direction of said step-and-scan type projection exposure apparatus.