US 2006/0232296 A1Published application

Fast processing path using field programmable gate array logic unit

AssigneeKilopass Technologies, Inc.

InventorsMan Wang, Suhail Zain

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Abstract

The described embodiments relate to the general area of Field Programmable Gate Arrays (FPGAs), and, in particular, to the architecture and the structure of the building blocks of the FPGAs. Proposed logic units, as separate units or a chain of units, which are mainly comprised of look-up tables, multiplexers, and latches, implement different mathematical and logical functions. Having two outputs, the embodiments of the logic unit can operate in a split mode and perform two separate logic and/or arithmetic functions at the same time. Chains of the proposed logic units, wherein every other unit is clocked by one of the two half clock cycles and utilizes local interconnections instead of traditional routing channels, add to efficiency and speed, and reduce required real estate.

Claims20

Dependent claims

A field programmable gate array (FPGA) logic head, comprising:

two 3-input look-up tables, six data input ports, four control signals, two data output ports, two latches, two dynamic (standard) multiplexers, and seven hard-wired (programmable) multiplexers;
and
a configuration, wherein:
3-input look-up tables, in a split mode, are capable of being used as separate look-up tables, with or without latched outputs;
latches are capable of being used either as separate latches or as one flip-flop;
3-input look-up tables are capable of forming a 4-input look-up table, wherein the 4-input look-up table can be utilized separately, in connection with a latch, or in connection with a flip-flop;
a combination of a 3-input look-up table and a latch is capable of being utilized as a unit in a cascade chain of such units, where every other latch in the chain latches the output of its corresponding look-up table for one half of a clock cycle and the other latches of the chain latch the outputs of their corresponding look-up tables for the other half of the clock cycle;
a combination of the 4-input look-up table and a latch is capable of being utilized as a unit in a cascade chain of such units, where every other latch in the chain latches the output of its corresponding look-up table for one half of a clock cycle and the other latches of the chain latch the outputs of their corresponding look-up tables for the other half of the clock cycle;
and
a grouping of a combinational logic and a latch of the logic head is capable of being utilized as a unit in a cascade chain of such units, where every other latch in the chain latches the output of its corresponding combinational logic for one half of the clock cycle and the other latches of the chain latch the outputs of their corresponding combinational logic for the other half of the clock cycle.

7 more elements

A field programmable gate array (FPGA), comprising:

two n-input look-up tables, two registers, and multiple multiplexers;
and
a configuration, wherein:
n-input look-up tables, in a split mode, are capable of being used as separate combinatorial logic gates, with or without registered outputs;
registers are capable of being used separate from the look-up tables;
registers are capable of being used in combination to form a flip-flop;
the two n-input look-up tables are capable of forming one (n+1)-input look-up table, wherein the (n+1)-input look-up table can be utilized separately, in connection with a register, or in connection with the flip-flop;
a combination of an n-input look-up table and a register is capable of being utilized in a cascade chain of such combinations, where every other register in the chain stores the output of its corresponding look-up table for one half of a clock cycle and the other registers of the chain store the outputs of their corresponding look-up tables for the other half of the clock cycle;
and
a grouping of a combinational logic and a register of the logic head is capable of being utilized in a cascade chain of such groupings, where every other register in the chain stores the output of its corresponding combinational logic for one half of the clock cycle and the other registers of the chain store the outputs of their corresponding combinational logic for the other half of the clock cycle.

7 more elements

Dependencies are inferred from the claim text.