Thin multiple semiconductor die package
AssigneeAdvanced Interconnect Technologies Limited
InventorsFrank Juskey, Daniel Lau
Life of this patent
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AssigneeAdvanced Interconnect Technologies Limited
InventorsFrank Juskey, Daniel Lau
Estimating the term…
A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from a first surface (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected to the leads (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion of the leads (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substantially coplanar and are exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) of the leads form a cavity (102). The semiconductor die packages (200, 300, 400) are stacked such that at least a portion of the encapsulant (50) is disposed in the cavity of a next higher semiconductor die package (200, 300, 400) in the stack.
A semiconductor die assembly (200, 300, 400), comprising:
A method for forming a semiconductor die assembly (200, 300, 400), the method comprising:
Dependencies are inferred from the claim text.