Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance

A 6T-SRAM cell semiconducting structure comprising:

• a substrate comprising an SOI region and a bulk-Si region, wherein said SOI region and said bulk-Si region have a same or differing crystallographic orientation;
• an isolation region separating said SOI region from said bulk-Si region;
• a well region underlying a device in said bulk-Si region and a contact to said well region, wherein said contact stabilizes floating body effects and provides a means for adjusting the threshold voltages in FETs in the bulk-Si region through the application of a bias voltage;
• and
• a device configuration selected from the group consisting of (a) two pass-gate NFET devices located in the bulk-Si region and two pull-down NFET devices and two pull-up pFET devices located in the SOI region, (b) two pass-gate nFET devices and two-pull down NFET devices located in the bulk-Si region and two pull-up pFET devices located in the SOI region, (c) two pull-down NFET devices located in the bulk-Si region and two pass-gate NFET devices and two pull-up pFET devices located in the SOI region and (d) two pull-up pFET devices located in the bulk-Si region and a pull-down NFET and a pass-gate nFET located in the SOI region.