SOI SRAM products with reduced floating body effect and the method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorPing-Wei Wang
Life of this patent
Estimating the term…
Abstract
A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate contacts in the peripheral region of the memory device, and a plurality of second substrate contacts in the memory region of the SOI structure, wherein the first substrate contacts and the second substrate contacts are formed in and over the semiconductor film and in the insulating layer and are electrically connected to the substrate of the SOI structure.
Claims20
A memory device formed on a semiconductor-on-insulator (SOI) structure, the SOI structure comprising a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer, the memory device comprising:
- a memory array in a memory region of the SOI structure;
- a plurality of first substrate contacts in a peripheral region of the memory device;
- and
- a plurality of second substrate contacts in the memory region of the SOI structure,
- wherein the first substrate contacts and the second substrate contacts are formed in the semiconductor film and in the insulating layer and are electrically connected to the substrate of the SOI structure.
A memory device formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor film on the insulating layer, the memory device comprising:
- a memory array in a memory region of the SOI structure, including
- a global word line,
- a plurality of memory blocks, each memory block including
- a plurality of memory banks each including a smaller memory array,
- a plurality of local word line decoders connected to the global word line, and
- a plurality of bit line sense amplifier (BL-SA) circuits,
- wherein each memory bank corresponds to one of the local word line decoders and at least one of the BL-SA circuits, and
- a plurality of first substrate contacts;
- and
- a plurality of second substrate contacts in the peripheral regions of the memory device,
- wherein the first substrate contacts and the second substrate contacts are formed in the semiconductor film and in the insulating layer and are electrically connected to the semiconductor substrate of the SOI structure.
Dependencies are inferred from the claim text.