Merged MOS-bipolar capacitor memory cell
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and a collector region. The base region for the vertical bi-polar transistor serves as the source region for the vertical MOS transistor. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical MOS transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor. The base region for the vertical bi-polar transistor is coupled to a write data word line.
Claims25
An electronic system, comprising:
- a processor;
- and
- a memory operably coupled to the processor, wherein the memory includes a memory array including:
- a number of memory cells formed on a substrate, wherein each memory cell includes:
- a MOS transistor having a source region, a drain region, and a floating body region therebetween;
- a bi-polar transistor having an emitter region, a base region and a collector region, the base region for the bi-polar transistor adapted to serve as the source region for the MOS transistor;
- a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the MOS transistor;
- and
- a floating body back gate opposing the floating body region on a second side of the MOS transistor;
- and
- a write data word line coupled to the base region of each memory cell along columns of the array.
An electronic system, comprising:
- a processor;
- and
- a memory operably coupled to the processor, wherein the memory includes a memory array including:
- a number of memory cells formed on a substrate, wherein each memory cell includes:
- a MOS transistor having a source region, a drain region, and a body region therebetween;
- a bi-polar transistor having an emitter region, a base region and a collector region;
- and
- wherein the collector region for the bi-polar transistor is adapted to serve as the body region for the MOS transistor;
- and
- a write data word line coupled to the base region of each memory cell along columns of the array.
An electronic system, comprising:
- a processor;
- and
- a memory operably coupled to the processor, wherein the memory includes a memory array including:
- a number of memory cells formed on a substrate, wherein each memory cell includes:
- a semiconductor pillar, including:
- a first conductivity region with n-type doping on a substrate;
- a second conductivity region with p-type doping on the first conductivity region;
- a third conductivity region with n-type doping on the second conductivity region;
- and
- a fourth conductivity region with p-type doping on the third conductivity region;
- a gate adjacent to and separated from the third conductivity region on a first side of the semiconductor pillar;
- and
- a body capacitor, including the third conductivity region and a capacitor plate adjacent to and separated from the third conductivity region on a second side of the semiconductor pillar;
- and
- a write data word line coupled to the second conductivity region of each memory cell along columns of the array.
An electronic system, comprising:
- a processor;
- and
- a memory operably coupled to the processor, wherein the memory includes a memory array including:
- a number of memory cells formed on a substrate, wherein each memory cell includes:
- a semiconductor pillar, including:
- an n+ conductivity region to function as an emitter of a bi-polar transistor;
- a p conductivity region on the n+ conductivity region, the p conductivity region to function as a base region for the bi-polar transistor;
- an n conductivity region on the p conductivity region, the n conductivity region to function as a collector region of the bi-polar transistor and as a body region of a PMOS transistor;
- and
- a p+ conductivity region on the n conductivity region;
- a gate for the PMOS transistor adjacent to and separated from the n conductivity region on a first side of the semiconductor pillar;
- and
- a write data word line coupled to the base region of each memory cell along columns of the array.
Dependencies are inferred from the claim text.