Semiconductor device including ROM interface pad
AssigneeSamsung Electronics Co., Ltd.
InventorsJin-Hyeok Choi, Sam-Yong Bahng
Life of this patent
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Abstract
A semiconductor device comprises a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern, a second circuit pattern for testing the semiconductor device, the second circuit formed on a predetermined region of the multilayer, an inter-metal insulating layer formed on the second circuit pattern, a plurality of via contacts formed in the inter-metal insulating layer, and a plurality of ROM interface pads disposed on the inter-metal insulating layer, wherein the plurality of ROM interface pads are electrically connected with the second circuit pattern through the plurality of via contacts, and are separated from one another.
Claims29
A semiconductor device comprising:
- a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern;
- a second circuit pattern for testing the semiconductor device, the second circuit pattern formed on a predetermined region of the multilayer;
- an inter-metal insulating layer formed on the second circuit pattern;
- a plurality of via contacts formed in the inter-metal insulating layer;
- and
- a plurality of ROM interface pads disposed on the inter-metal insulating layer, wherein the plurality of ROM interface pads are electrically connected with the second circuit pattern through the plurality of via contacts, and are separated from one another.
A semiconductor device comprising:
- a processor unit formed using a plurality of layers on a substrate;
- a test circuit block formed using the plurality of layers, the test circuit block receiving test data from a predetermined data storage device located outside of the semiconductor device and transferring the test data to the processor unit;
- an inter-metal insulating layer formed on the test circuit block, the inter-metal insulating layer comprising a plurality of via contacts;
- a first plurality of pads for receiving a voltage, a control signal, and input/output data;
- and
- a second plurality of pads disposed on the inter-metal insulating layer, wherein the second plurality of pads are electrically connected to the test circuit block through the plurality of via contacts, and are separated from one another.
A test printed circuit board (PCB) comprising:
- an external memory device storing command codes to be verified;
- and
- a semiconductor device comprising a processor device receiving the command codes of the external memory device and validating the command codes,
- wherein the semiconductor device and the external memory device are mounted on the test PCB, and the external memory device is electrically connected to the test PCB.
A semiconductor device comprising:
- a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern for performing a predetermined function;
- a second circuit pattern for testing the semiconductor device formed on a predetermined region of the multilayer;
- an inter-metal insulating layer formed on the second circuit pattern;
- a plurality of via contacts formed on the inter-metal insulating layer;
- a first metal layer formed on a pad metal layer in a pad region;
- and
- a plurality of ROM interface pads disposed on the inter-metal insulating layer, wherein the ROM interface pads are electrically connected to the second circuit pattern through the plurality of via contacts, and separated from one another.
Dependencies are inferred from the claim text.