Step-embedded SiGe structure for PFET mobility enhancement
AssigneeToshiba America Electronic Components, Inc.
InventorYusuke Kohyama
Life of this patent
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Abstract
A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.
Claims20
A semiconductor device having a PFET, the PFET comprising:
- a silicon body having a PFET channel;
- a first SiGe layer portion disposed on a first side of the channel and having a multi-stepped boundary facing the channel;
- and
- a second SiGe layer portion disposed on a second opposite side of the channel and having a multi-stepped boundary facing the channel.
A semiconductor device having a PFET, the PFET comprising:
- a gate;
- a silicon body, wherein the gate is disposed on the silicon body, and wherein the silicon body has, on each of two opposing sides of the gate:
- a first surface,
- a second surface extending at an angle from the first surface,
- a third surface extending at an angle from the second surface and spaced from the first surface by at least the second surface, and
- a fourth surface extending at an angle from the third surface and spaced from the first and second surfaces by at least the third surface;
- and
- a SiGe layer disposed on the first, second, third, and fourth surfaces of the silicon body on each of the two opposing sides of the gate.
A method for manufacturing a semiconductor device, comprising:
- providing a silicon body;
- forming a gate on the silicon body;
- removing a portion of the silicon body such that the silicon body has a multi-stepped boundary on each of two opposing sides of the gate;
- and
- forming an SiGe layer on the multi-stepped boundary of the silicon body on each of the two opposing sides of the gate.
A method for manufacturing a semiconductor device, comprising:
- providing a silicon body;
- forming a gate on the silicon body;
- removing a portion of the silicon body such that the silicon body has, on each of two opposing sides of the gate:
- a first surface,
- a second surface extending at an angle from the first surface,
- a third surface extending at an angle from the second surface and spaced from the first surface by at least the second surface, and
- a fourth surface extending at an angle from the third surface and spaced from the first and second surfaces by at least the third surface;
- and
- forming a SiGe layer on the first, second, third, and fourth surfaces of the silicon body on each of the two opposing sides of the gate.
Dependencies are inferred from the claim text.