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US 2006/0231734 A1Published application
Generation and storage of column offsets for a column parallel image sensor
AssigneeMicron Technology, Inc.
InventorSteven Shaw
Life of this patent
Estimating the term…
Abstract
The plural signal chains of an imaging device are calibrated in the digital domain. The pixel array of the imaging device includes a row of calibration pixels. The column circuitry, prior to reading a row of pixels, reads the row of calibration pixels in order to obtain a set of column offsets. The row of pixels is read and processed to produce a corresponding plurality of digital values. The set of column offsets are applied to the digital values to compensate for response differences among the signal chains.
Claims29
A column circuit for an imager, comprising:
- a plurality of column readout lines;
- a plurality of signal chains, each signal chain being associated with N of said plurality of column readout lines, where N is an integer greater than or equal to one;
- at least one memory, said at least one memory containing N respective memory storage areas per signal chain, each of said memory storage areas for storing an offset value associated with a respective one of said plurality of column readout lines;
- and
- a control circuit, for processing said offset values and said digital pixel readout values processed by said signal chains.
2 more elements
An imager, comprising:
- a pixel array, said pixel array comprising:
- imaging pixels arranged in a plurality of columns and a plurality of rows;
- and
- a row of calibration pixels;
- and
- a column circuit, for receiving analog signals from a selected row of pixels in said pixel array and producing a corresponding set of digital pixel signals, said column circuit comprising:
- a plurality of column readout lines;
- a plurality of signal chains, each signal chain being associated with N of said plurality of column readout lines, where N is an integer greater than or equal to one;
- at least one memory, said at least one memory containing N respective memory storage areas per signal chain, each of said memory storage areas for storing an offset value associated with a respective one of said plurality of column readout lines;
- and
- a control circuit, for processing said offset values and said digital pixel readout values processed by said signal chains.
8 more elements
An imaging system, comprising:
- a processor;
- and
- an imaging device, coupled to said processor, said imaging device comprising:
- a pixel array, said pixel array comprising:
- imaging pixels arranged in a plurality of columns and a plurality of rows;
- and
- a row of calibration pixels;
- and
- a column circuit, for receiving analog signals from a selected row of pixels in said pixel array and producing a corresponding set of digital pixel signals, said column circuit comprising:
- a plurality of column readout lines;
- a plurality of signal chains, each signal chain being associated with N of said plurality of column readout lines, where N is an integer greater than or equal to one;
- at least one memory, said at least one memory containing N respective memory storage areas per signal chain, each of said memory storage areas for storing an offset value associated with a respective one of said plurality of column readout lines;
- and
- a control circuit, for processing said offset values and said digital pixel readout values processed by said signal chains.
11 more elements
A method of operating an imager having an array of pixels arranged in rows and columns, said method comprising the acts of:
- (a) at a first time, reading, in accordance with a current gain, a plurality of calibration values from a row of calibration pixels of said array;
- (b) determining a reference value from said plurality of calibration values;
- (c) at a second time after said first time, reading, in accordance with said current gain, a second plurality of calibration values from said row of calibration pixels of said array;
- (d) calculating and storing, for each column, an offset value based on said reference value and said plurality of calibration values;
- (e) setting a target row to a current row;
- (f) reading, in accordance with said current gain, a plurality of signal values from said target row;
- and
- (g) respectively applying said plurality of offset values to said plurality of signal values.
5 more elements
A method for forming an imaging circuit, comprising:
- providing a semiconductor substrate;
- forming, over said semiconductor substrate, a pixel array, said pixel array comprising:
- imaging pixels arranged in a plurality of columns and a plurality of rows;
- and
- a row of calibration pixels;
- and
- forming, over said semiconductor substrate, a column circuit for receiving analog signals from a selected row of pixels in said pixel array and producing a corresponding set of digital pixel signals, said column circuit comprising:
- a plurality of column readout lines;
- a plurality of signal chains, each signal chain being associated with N of said plurality of column readout lines, where N is an integer greater than or equal to one;
- at least one memory, said at least one memory containing N respective memory storage areas per signal chain, each of said memory storage areas for storing an offset value associated with a respective one of said plurality of column readout lines;
- and
- a control circuit, for processing said offset values and said digital pixel readout values processed by said signal chains.
9 more elements
Dependencies are inferred from the claim text.