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US 2006/0225074 A1Published application
Method and apparatus for communication between two or more processing elements
AssigneeIntel Corporation
InventorsKushagra Vaid, John Crawford, Allen Baum
Life of this patent
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Abstract
A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.
Claims30
An apparatus comprising:
- a first register to store a plurality of bits corresponding to any of a plurality of processing elements, any of the plurality of bits to be accessed by any of the plurality of processing elements directly.
A system comprising:
- a master processing element comprising a plurality of reassignable bits;
- a plurality of slave processing elements to perform a plurality of tasks assigned by the master processing element, the plurality of slave processing elements to send a completion message to the master processing element after completing the plurality of tasks, the master processing element to record the completion of the plurality of tasks within the plurality of reassignable bits.
A method comprising:
- assigning a plurality of bits within a processor register to a first plurality of processing elements to perform a plurality of concurrent tasks;
- updating the plurality of bits within the processor register as the first plurality of processing elements complete the plurality of concurrent tasks;
- indicating to the first plurality of processing elements when all processing elements have completed the plurality of concurrent tasks;
- reassigning the plurality of bits to a second plurality of processing elements after the first plurality of processing elements have completed the plurality of concurrent tasks.
1 more element
A machine-readable medium having stored thereon at least one instruction, which if executed by a machine causes the machine to perform a method comprising:
- assigning a plurality of register bits to a plurality threads within a multi-threaded program;
- initializing the plurality of register bits to a first value;
- recording a number of completed tasks of a first set of tasks associated with the plurality of threads;
- changing the assignment of the plurality of register bits after the first set of tasks are complete if the number of the plurality of threads changes.
1 more element
Dependencies are inferred from the claim text.