System for predictive processor component suspension and method thereof
AssigneeAdvanced Micro Devices, Inc.
InventorDan Feekes
Life of this patent
Estimating the term…
Abstract
An instruction cycle is determined from instructions stored in a cache, where the instruction cycle represents the sequence of instructions predicted to be executed by the processing device that are resident in the cache. The duration of the instruction cycle is estimated and one or more components of the processing device that are not expected to be used during the instruction cycle may be suspended for a portion or all or the duration. The components may be suspended by, for example, clock gating or by isolating the components from one or more power domains.
Claims21
A method comprising:
- receiving a plurality of instructions;
- identifying one or more components of a processor that are expected to be unused during an execution of a sequence of instructions from the plurality of instructions;
- and
- suspending at least one of the one or more identified components of the processor during an execution of at least a portion of the sequence of instructions by the processor.
A method comprising:
- storing a plurality of instructions in a cache;
- identifying one or more components of the processor expected to be unused during an execution of a sequence of instructions of the plurality of instructions by a processor;
- estimating a duration before an instruction not in the sequence of instructions is to be requested for execution by the processor;
- and
- suspending, based on the duration, at least one of the one or more identified components of the processor during an execution of at least a portion of the sequence of instructions by the processor.
A processor comprising:
- a plurality of components;
- storage means for storing a plurality of instructions;
- means for identifying one or more components of the plurality of components that are expected to be unused during an execution of a sequence of instructions of the plurality of instructions by the processor;
- and
- means for suspending at least one of the one or more identified components during an execution of at least a portion of the sequence of instructions by the processor.
A processor comprising:
- a plurality of components;
- a decode cache to store a plurality of instructions to be executed by the processor;
- and
- a controller to:
- identify one or more of the plurality of components expected to be unused during an execution of a sequence of instructions of the plurality of instructions by the processor;
- and
- initiate a suspension of at least one of the identified one or more components for at least a portion of the execution of the sequence of instructions by the processor.
Dependencies are inferred from the claim text.