Method and apparatus for laying out cells in a semiconductor device

An apparatus for generating layout data to lay out a plurality of macro cells in a core region of a semiconductor device, the apparatus comprising:

• a memory;
• an auxiliary layout region calculation circuit for determining auxiliary layout regions respectively corresponding to the macro cells, and for storing information of the auxiliary layout regions in the memory;
• a maximum standard cell calculation circuit for calculating the area of a maximum standard cell region by subtracting the area of the macro cells and the area of the auxiliary layout regions from the area of the core region, and for storing the area of the maximum standard cell region in the memory;
• an actual standard cell calculation circuit for calculating the area of an actual standard cell region in which layout of standard cells is enabled in the core region in accordance with a floor plan result in which the macro cells are laid out, and for storing the area of the standard cell region in the memory;
• a dead space calculation circuit for reading the area of the maximum standard cell region and the area of the actual standard cell region from the memory to calculate a dead space percentage of the floor plan from the area of the maximum standard cell region and the area of the actual standard cell region;
• a dead space determination circuit for comparing the dead space percentage with a reference value to determine whether or not the layout of the macro cells must be changed;
• and
• a floor plan generation circuit for generating a floor plan based on the determination result of the dead space determination circuit by changing the layout of the macro cells so that the dead space percentage becomes less than or equal to the reference value.