Various methods and apparatuses for flexible hierarchy grouping
OwnerKamil Synek, Jay Tomlinsoninventors
Life of this patent
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Abstract
Methods and apparatuses are described for incorporating floor planning information into a configuration process by generating a definition of a floor plan grouping of interconnect components during a front-end view design process for the interconnect. Further, a user is permitted to combine components from separate IP block representations of interconnects during the front-end view design process, based upon physical location of the grouping of the components making up the interconnects on the chip.
Claims24
A machine readable medium that contains instructions, which when executed by the machine cause the machine to perform the following operations, comprising:
- permitting a user to incorporate floor planning information into a electronic system configuration process by generating a definition of a floor plan of groups of interconnect components during a front-end view design process for the electronic system;
- and
- permitting a user to combine components from separate Intellectual Property (IP) block representations of interconnects during the front-end view design process, based upon a physical location on a chip of the groups of components making up the interconnects on the chip.
A method, comprising:
- incorporating floor planning information into a electronic system configuration process by generating a definition of a floor plan of groups of interconnect components during a front-end view design process for the electronic system;
- and
- combining components from separate Intellectual Property (IP) block representations of interconnects during the front-end view design process, based upon a physical location on a chip of the groups of components making up the interconnects on the chip.
A System on Chip, comprising:
- a plurality of IP cores,
- a first interconnect IP core facilitating communications between a first set of Intellectual Property (IP) cores;
- and
- a second interconnect IP core facilitating communications between a second set of IP cores as well as communications between the first and second interconnect cores, wherein components from the IP cores representing the first and second interconnects are combined during the front-end view design process, based upon a physical location on a chip of the groups of components making up the first and second interconnects on the chip.
An apparatus comprising:
- means for incorporating floor planning information into a electronic system configuration process by generating a definition of a floor plan of groups of interconnect components during a front-end view design process for the electronic system;
- and
- means for combining components from separate Intellectual Property (IP) block representations of interconnects during the front-end view design process, based upon a physical location on a chip of the groups of components making up the interconnects on the chip.
Dependencies are inferred from the claim text.