Semiconductor device and scan test method
AssigneeNEC Electronics Corporation
InventorYoshiaki Sera
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a clock signal separating circuit and a logic circuit. The clock signal separating circuit separates a clock signal into a first separation clock signal and a second separation clock signal and to supply the second separation clock signal to a test circuit. The logic circuit generates an output clock signal from the first separation clock signal and a first scan clock signal to the test circuit. A second scan clock signal is supplied to the test circuit.
Claims10
A semiconductor device comprising:
- a clock signal separating circuit configured to separate an external clock signal into a first separation clock signal and a second separation clock signal and to supply said second separation clock signal to a test circuit;
- and
- a logic circuit configured to generate an output clock signal from said first separation clock signal and a first scan clock signal to said test circuit, wherein a second scan clock signal is supplied to said test circuit.
A method of carrying out a delay test of a semiconductor device, comprising:
- providing a scan test path which includes a flip-flop circuits and an internal circuit as a test target;
- carrying out a shifting operation in said scan test path in a first shift mode;
- supplying an external clock signal in a second shift mode;
- taking a data in said scan test path in a capture mode by using a part of said external clock signal;
- and
- carrying out a shifting operation in said scan test path in a third shift mode.
A semiconductor device having a scan path test circuit, comprising:
- a scan path flip-flop configured to carry out a shift mode operation in response to a 2-phase clock signal of a master clock signal and a slave clock signal and a capture mode operation in response to a system clock signal;
- and
- a separating circuit configured to separate an external clock signal into said slave clock signal and said system clock signal.
Dependencies are inferred from the claim text.