Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits
AssigneeAltera Corporation
InventorsJames Schleicher, David Karchmer
Life of this patent
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Abstract
Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.
Claims21
A method of producing information for specifying the configuration of a structured ASIC that will be functionally equivalent to a programmed FPGA performing a user's logic design comprising:
- synthesizing the user's logic design for implementation in the FPGA;
- converting a synthesis that results from the synthesizing to a modified synthesis that is suitable for structured ASIC implementation;
- performing a place and route operation on the modified synthesis to produce a further synthesis adapted for placement on a structured ASIC;
- and
- further converting the further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC.
A method of implementing a user's logic design in a programmed FPGA and a functionally equivalent structured ASIC comprising:
- synthesizing the user's logic design for implementation in the FPGA;
- performing a first place and route operation on a synthesis that results from the synthesizing to produce a first further synthesis adapted for determining how the FPGA should be programmed;
- converting a synthesis that results from synthesizing the user's logic design for implementation in the FPGA to a modified synthesis that is suitable for structured ASIC implementation;
- performing a second place and route operation on the modified synthesis to produce a second further synthesis adapted for placement on a structured ASIC;
- and
- converting the second further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC.
A method of implementing a logic design in a structured ASIC, for which a functionally equivalent FPGA can be made, comprising:
- producing an FPGA synthesis of the logic design;
- converting the FPGA synthesis to a structured ASIC synthesis;
- performing a place and route operation on the structured ASIC synthesis to produce a further synthesis adapted for placement on a structured ASIC;
- and
- converting the further synthesis to a specification for the structured ASIC that includes identifications of physical circuits that are to be used in producing the structured ASIC.
Dependencies are inferred from the claim text.