Method and apparatus of optimizing the io collar of a peripheral image
AssigneeInternational Business Machines Corporation
InventorsWai Chung-Maloney, Haruo Ito, Douglas Stout
Life of this patent
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Abstract
An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar. All the IO cells may be rotated, or a combination of rotated and non-rotated IO cells may form the IO collar. For each edge of the IC chip having rotated IO cells, each edge may have the same number of stacks of IO cells or a different number of stacks of IO cells.
Claims20
A method of reducing the die size of an IC chip, comprising the steps of:
- determining a minimum number of IO cells required by the IC chip;
- arranging the minimum number of IO cells in rows of IO cells around edges of the IC chip where at least one of the rows of IO cells comprises rotated IO cells;
- and
- completing any incomplete row of IO cells of the rows of IO cells by adding unused IO cells to the incomplete row of IO cells.
A method of arranging IO cells in an IO collar, comprising the steps of:
- determining an aspect ratio for IO cells;
- determining a minimum number of functioning IO cells needed by an IC chip;
- determining a total number of IO cells to fit along each edge of the IC chip;
- determining an IO cell stack height for each edge of the IC chip based on the minimum number of functioning IO cells needed by a the IC chip and the total number of IO cells to fit along an edge of the IC chip;
- arranging IO cells in rows along each edge of the IC chip;
- and
- completing any incomplete rows of IO cells by adding unused IO cells to the incomplete rows of IO cells.
An IO collar, comprising:
- a first row of IO cells distributed along a first edge of an IC chip, wherein the first row of IO cells comprises non-rotated IO cells;
- a second row of IO cells distributed along at least a second edge of the IC chip, wherein the second row comprises rotated IO cells;
- a third row of IO cells distributed along a third edge of the IC chip;
- and
- a fourth row of IO cells distributed along a fourth edge of the IC chip.
Dependencies are inferred from the claim text.