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US 2006/0225002 A1Published application
Circuit having hardware threading
AssigneeTufts University
InventorsSoha Hassoun, Brian Swahn
Life of this patent
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Abstract
Hardware threading optimizes use of hardware resources in a dynamic workload environment. Unutilized hardware resources are dynamically borrowed to increase throughput performance and/or power savings by enabling parallel processing of application pipeline stages.
Claims22
A method of designing a hardware threaded circuit architecture, comprising:
- determining a total area available for processing elements;
- determining a set of task arrival times for tasks to be processed by the processing elements;
- determining a number of possible implementations for the processing elements within the area available, each of the possible implementations having a corresponding number of processing elements;
- interconnecting first and second ones of the processing elements;
- determining overall system wait times for the possible implementations;
- and
- selecting a first one of the possible implementations based upon the overall system wait times.
4 more elements
The method according to claim 6, further including determining a number of pipeline stages based upon the state-based flow for the application.
A method of scheduling processing in a hardware threaded circuit, comprising:
- receiving inputs corresponding to unthreaded processing of an application;
- receiving information including processing element resources, a number of processing elements, and a window size corresponding to a number of downstream processing states to be examined;
- and
- generating a hardware threaded schedule for processing the application with at least first and second one of the processing elements being interconnected to enable dynamic resource sharing.
1 more element
A hardware threaded circuit system, comprising:
- a memory;
- a task manager coupled to the memory;
- and
- a plurality of processing elements coupled to the task manager, wherein first and second ones of the plurality of processing elements are interconnected for hardware threaded processing to enable dynamic borrowing of processing resources associated with the second one of the plurality of processing elements by the first one of the plurality of processing elements.
1 more element
Dependencies are inferred from the claim text.