Mechanism for implementing redundancy to mask failing SRAM
AssigneeIntel Corporation
InventorMarcin Nowicki
Life of this patent
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Abstract
In some embodiments, an apparatus to implement redundancy for failure masking in memory is disclosed. The apparatus comprises a built-in self test (BIST) log to store BIST data representing faulty columns of a memory, a redundancy configuration logic to generate one or more select signals based on the BIST data, an input shifter to map input data to one or more redundant columns of the memory, based on the one or more select signals, to avoid the faulty columns, and an output shifter to map output data from the one or more redundant columns of the memory, based on the one or more select signals, by bypassing the faulty columns. In one embodiment the memory is a static random access memory (SRAM). Other embodiments are also described.
Claims21
An apparatus, comprising:
- a built-in self test (BIST) log to store BIST data representing faulty columns of a memory;
- redundancy configuration logic to generate one or more select signals based on the BIST data;
- an input shifter to map input data to one or more redundant columns of the memory, based on the one or more select signals, to avoid storing the input data to the faulty columns;
- and
- an output shifter to map output data from the one or more redundant columns of the memory, based on the one or more select signals, by bypassing the faulty columns.
A method, comprising:
- receiving built-in self test (BIST) data representing faulty columns in a memory;
- mapping input data to one or more redundant columns of the memory to avoid the faulty columns of the memory based on the BIST data;
- and
- mapping the redundant columns of the memory to output data by bypassing the faulty columns of the memory based on the BIST data.
A system, comprising:
- a controller hub;
- a processor coupled to the controller hub including a memory controller to control a memory;
- and
- logic to configure the memory, including:
- a built-in self test (BIST) log to store BIST data representing faulty columns of the memory;
- a redundancy configuration logic to generate one or more select signal based on the BIST data;
- an input shifter to map input data to one or more redundant columns of the memory, based on the one or more select signals, to avoid storing the input data to the faulty columns;
- and
- an output shifter to map output data from the one or more redundant columns of the memory, based on the one or more select signals, by bypassing the faulty columns.
Dependencies are inferred from the claim text.