Apparatus and method to generate and save run time data
AssigneeInternational Business Machines Corporation
InventorsCharles Cardinell, Roger Hathorn, Man Ma, Kimberly Thomas
Life of this patent
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Abstract
A method is disclosed to generate and save run time data. The method supplies an embedded device comprising a processor which includes a processor cache, memory, a hardware trace facility comprising a plurality of data buffers, where the embedded device is capable of communicating with one or more host adapter ports. The method generates a trace entry, stores that trace data entry in the processor cache, and then writes the trace data entry to the plurality of data buffers.
Claims20
A method to generate and save run time data, comprising the steps of:
- supplying an embedded device comprising a processor, a processor cache, memory, a hardware trace facility comprising a plurality of data buffers, a first bus interconnecting said hardware trace facility and said memory, and a second bus interconnecting said processor and said hardware trace facility, wherein said embedded device is capable of communicating with one or more host adapter ports;
- generating trace data by said processor, without interrupting said first bus or said second bus;
- storing said trace data in said processor cache, without interrupting said first bus or said second bus;
- writing said trace data to said plurality of data buffers comprising a plurality of FIFOs, without interrupting said first bus.
An article of manufacture comprising a processor, a processor cache, memory, a hardware trace facility comprising a plurality of FIFO data buffers, a first bus interconnecting said hardware trace facility and said memory, and a second bus interconnecting said processor and said hardware trace facility, wherein said article of manufacture is capable of communicating with one or more host adapter ports, and a computer useable medium having computer readable program code disposed therein to generate and save run time data, the computer readable program code comprising a series of computer readable program steps to effect:
- generating trace data, without interrupting said first bus or said second bus;
- storing said trace data in said processor cache, without interrupting said first bus or said second bus;
- writing said trace data to said plurality of FIFOs, without interrupting said first bus.
A computer program product usable with a programmable computer processor to generate and save run time data using an embedded device comprising a processor, a processor cache, memory, a hardware trace facility comprising a plurality of FIFO data buffers, a first bus interconnecting said hardware trace facility and said memory, and a second bus interconnecting said processor and said hardware trace facility, wherein said embedded device is capable of communicating with one or more host adapter ports, comprising:
- computer readable program code which causes said programmable computer processor to generate trace data by said processor, without interrupting said first bus or said second bus;
- computer readable program code which causes said programmable computer processor to store said trace data in said processor cache, without interrupting said first bus or said second bus;
- computer readable program code which causes said programmable computer processor to write said trace data to said plurality of FIFOs, without interrupting said first bus.
The computer program product of claim 18, wherein the computer readable program code which causes said programmable computer processor to write trace data to said plurality of data buffers step further comprises computer readable program code which causes said programmable computer processor to:
- issue a data cache block flush command;
- write up to the size of the cache line of data from said cache line to said plurality of FIFOs.
Dependencies are inferred from the claim text.