Clock distribution for interconnect structures
AssigneeIntel Corporation
InventorMartin Denham
Life of this patent
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Abstract
Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure propagates a master clock signal serially through the clock units of the connector circuits to generate a number of different input clock signals. The timing provided by each of the clock units is based on the timing of one of the input clock signals. Other embodiments are described and claimed.
Claims28
An interconnect structure comprising:
- a first clock path including a first buffer to propagate an input clock signal to provide a first internal clock signal;
- a second clock path including a plurality of buffers to propagate the input clock signal to provide a second internal clock signal;
- a first data transfer unit responsive to the first internal clock signal to transfer a message between a first data node and a second data node;
- and
- a second data transfer unit responsive to the second internal clock signal to transfer the message between the second data node and a third data node.
An interconnect structure comprising:
- a first connector circuit including a clock unit, the clock unit including a number of first buffers to propagate a first clock signal to generate a second clock signal, and a data transfer unit including a downstream data path to transfer a downstream message based on the first clock signal;
- a second connector circuit including a clock unit, the clock unit including a number of second buffers coupled in series with the first buffers to propagate the second clock signal to generate a third clock signal, and a data transfer unit including a downstream data path to transfer the downstream message based on the second clock signal;
- and
- a third connector circuit including a clock unit, the clock unit including a number of third buffers coupled in series with the second buffers to propagate the third clock signal, and a data transfer unit including a downstream data path to transfer the downstream message based on the third clock signal.
A system comprising:
- an interconnection to transfer data with multiple disks;
- and
- an integrated circuit chip coupled to the interconnection to transfer data with the multiple disks, the integrated circuit chip including:
- a plurality of devices;
- a clock generator to generate a master clock signal;
- and
- an interconnect structure to transfer data among the devices, the interconnect structure including a plurality of connector circuits, each of the connector circuits including a data transfer unit to transfer data, a clock unit to provide timing for a transfer of the data in the data transfer unit based on an input clock signal among a plurality of input clock signals, wherein a combination of the clock unit from each of the connector circuits forms a clock propagation path to serially propagate the master clock signal through the clock propagation path to provide the plurality of input clock signals.
A method comprising:
- propagating an input clock signal through a first number of buffers to generate a first internal clock signal;
- propagating the input clock signal through a second number of buffers to generate a second internal clock signal, wherein the second number of buffers is unequal to the first number of buffers;
- transferring a message from a first data node to a second data node based on timing of the first internal clock signal;
- and
- transferring the message from the second data node to a third data node based on timing of the second internal clock signal.
Dependencies are inferred from the claim text.