Semiconductor device with a power down mode

A semiconductor device with a power down mode, comprising:

• a power down detecting block for generating a power down mode signal by detecting if the power down mode is activated;
• a power source control block, which is actuated in response to the power down mode signal, for producing N number of power control signals each of which has a different ratio of an enable period to a disable period, N being an integer;
• N number of current saving blocks, each whose driving current requirement is reduced differently from each other in the power down mode;
• and
• N number of power switching blocks for controlling the power supply to the respective current saving blocks in response to the respective power control signals.

A power down mode supporting circuit, comprising:

• a power down detecting block for generating a power down mode signal by detecting if the power down mode is activated;
• a power source control block for producing a power control signal whose ratio of an enable period to a disable period is determined by the power down mode signal;
• and
• a power switching block for controlling the power supply to predetermined internal blocks of a semiconductor device in response to the power control signal.

A method for performing a power down mode in response to an external power down instruction from the outside of a semiconductor device to reduce the driving power supply to certain internal blocks designated as current saving blocks among internal blocks in the semiconductor device, which comprises the steps of:

• (a) detecting the power down mode in response to the power down instruction;
• (b) generating a power control signal having a pulse form whose ratio of an enable period to a disable period is determined whether or not the power down mode is activated;
• and
• (c) executing a switching operation to control the driving power supply to the current saving blocks.