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US 2006/0224906 A1Published application
Fault resilient boot of complex multi-rail processors in an information handling system
AssigneeDell Products L.P.
InventorAhsan Habib
Life of this patent
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Abstract
Fault resilient booting of complex multi-rail processors in an information handling system insures that all processor voltage rails are functioning properly before any processor fetches operating software code. In addition, the information handling system will automatically reboot when one or more of the processors fail during either a built-in self test (BIST) or a power failure provided that there is at least one good processor remaining in the information handling system to power-on self-test (POST) the information handling system again.
Claims20
A method for fault resilient boot of complex multi-rail processors in an information handling system, said method comprising the steps of:
- clearing processor DC-to-DC regulator failure status for all processors of an information handling system upon initial power-up;
- setting FRB_ENABLE when asserting PS_ON#, wherein FRB_ENABLE remains set until PS_ON# is de-asserted;
- setting a processor DC-to-DC regulator status as failed when an associated processor DC-to-DC regulator has failed;
- checking all processor DC-to-DC regulator status to determine if no processor DC-to-DC regulator has failed, then coupling all processor Powergood signals directly to SYSTEM_POWERGOOD generation logic;
- otherwise if at least one processor DC-to-DC regulator status is set as a failure, then masking the associated processor Powergood signal by forcing it indicate good status before coupling to the SYSTEM_POWERGOOD generation logic;
- and
- rebooting the information handling system with the remaining processors having good DC-to-DC regulators and disabling the processor having the failed DC-to-DC regulator.
4 more elements
A method for fault resilient boot of complex multi-rail processors in an information handling system, said method comprising the steps of:
- clearing processor DC-to-DC regulator failure status for all processors of an information handling system upon initial power-up;
- detecting when a PS_ON# is asserted;
- clearing a FRB_ENABLE upon detecting the asserted PS_ON# signal;
- detecting when a SYSTEM_POWERGOOD is asserted;
- setting the FRB_ENABLE upon detecting the asserted SYSTEM_POWERGOOD;
- determining if there are any DC-to-DC regulator failures;
- setting a respective status bit for each failed DC-to-DC regulator;
- disabling each processor coupled to a failed DC-to-DC regulator;
- masking the status bit for each failed DC-to-DC regulator;
- and
- rebooting the information handling system with only those processors coupled to good DC-to-DC regulators.
8 more elements
An information handing system having fault resilient boot of complex multi-rail processors, said system comprising:
- a plurality of processors, each of the plurality of processors having a first DC-to-DC regulator, each group of the plurality of processors having a common second DC-to-DC regulator, and all of the plurality of processors having a common third DC-to-DC regulator;
- means for clearing failure status of each of the first DC-to-DC regulators upon initial system power-up;
- means for detecting when a PS_ON# is asserted;
- means for clearing a FRB_ENABLE upon detection of the asserted PS_ON# signal;
- means for detecting when a SYSTEM_POWERGOOD signal is asserted;
- means for setting the FRB_ENABLE upon detecting the asserted SYSTEM_POWERGOOD signal;
- means for determining if there are any DC-to-DC regulator failures;
- means for setting a respective status bit for each failed DC-to-DC regulator;
- means for disabling each processor coupled to a failed DC-to-DC regulator;
- means for masking the status bit for each failed DC-to-DC regulator;
- and
- means for rebooting the information handling system with only those processors coupled to good DC-to-DC regulators.
9 more elements
An apparatus for fault resilient boot of complex multi-rail processors in an information handing system, comprising:
- a first bi-stable storage device having a clear input coupled to the PS_ON# output of the south bridge, a clock input coupled to a SYSTEM POWERGOOD signal and an output of an FRB_ENABLE signal;
- a plurality of second bi-stable storage devices, one for each of the first DC-to-DC regulators, for storing whether the respective first DC-to-DC regulator is functioning properly;
- a plurality of multiplexers, each of the plurality of multiplexers coupled to respective ones of the plurality of second bi-stable storage devices, wherein each of the plurality of multiplexers has an output of a conditioned DC-to-DC power good signal, wherein each of the conditioned DC-to-DC power good signals is either a power good signal representing a respective functioning first DC-to-DC regulator or a masked power good signal associated with a non-functioning first DC-to-DC regulator;
- and
- a logic circuit for generating the SYSTEM POWERGOOD signal when all conditioned DC-to-DC power good signals indicate a first logic level, wherein the first bi-stable storage device sets the FRB_ENABLE signal when the SYSTEM POWERGOOD signal is generated, and any of the plurality of processors coupled to non-functioning first DC-to-DC regulators will be disabled before the information handling system reboots.
2 more elements
An apparatus for fault resilient boot of complex multi-rail processors in an information handing system, comprising:
- means for storing failure status of each DC-to-DC regulator associated with a processor in a multiprocessor information handling system;
- means for clearing the failure status of each of the first DC-to-DC regulators upon initial system power-up;
- means for detecting when a PS_ON# is asserted;
- means for clearing a FRB_ENABLE upon detection of the asserted PS_ON# signal;
- means for detecting when a SYSTEM_POWERGOOD signal is asserted;
- means for setting the FRB_ENABLE upon detecting the asserted SYSTEM_POWERGOOD signal;
- means for determining if there are any DC-to-DC regulator failures;
- means for setting a status bit for each failed DC-to-DC regulator in the failure status storing means;
- means for disabling each processor coupled to a failed DC-to-DC regulator;
- means for masking the status bit for each failed DC-to-DC regulator;
- and
- means for rebooting the information handling system with only those processors coupled to good DC-to-DC regulators.
9 more elements
Dependencies are inferred from the claim text.