Acquiring instruction addresses associated with performance monitoring events

A system, comprising:

• a data store configured to store a record associated with an instruction processed by a pipelined processor;
• a performance monitoring logic configured to:
• detect an event caused by an instruction in the pipelined processor, where the event comprises one of, an instruction cache miss, a data cache miss, a pipeline hazard stall, and a pipeline instruction recirculate operation;
• to store in a record a processor state information concerning the pipeline when the event occurred;
• to write the record to the data store, where the record includes an instruction pointer field, a cycle count field, an instruction pointer validity field, a pipeline flush status field, and a data store freeze status field;
• and
• to selectively suspend the writing of records to the data store upon the occurrence of an identified event;
• and
• where the performance monitoring logic includes:
• an instruction pointer capturing logic configured to acquire the address of an instruction retiring from the pipeline and to add the address to the record;
• a cycle counting logic configured to count the number of cycles that occur between writes of records to the data store and to add the count to the record;
• an instruction pointer validity logic configured to capture a validity data concerning whether an instruction whose address is captured by the instruction capturing logic was retired from the pipeline when the pipeline was frozen and to add the validity data to the record;
• a flush status logic configured to capture a pipeline flush status data concerning whether a pipeline in the pipelined processor was flushed between writes of records to the data store and to add the pipeline flush status data to the record;
• and
• a freeze status logic configured to capture a freeze status data concerning whether record writing to the data store was frozen before a programmed overflow delay expired and to add the freeze status data to the record;
• and
• an instruction location logic configured to navigate records in the data store to determine the address of an instruction associated with the identified event by cycle counting to locate a first record associated with an instruction retiring from a pipeline in the pipelined processor when the identified event occurred and by retirement counting to locate a second record associated with an instruction executing at the pipeline stage when the identified event occurred, where the instruction location logic includes:
• a cycle counting logic configured to locate the first record by examining cycle count data in one or more records in the data store;
• and
• a retirement counting logic configured to locate the second record in the data store by examining retirement data in one or more records in the data store.

A method, comprising:

• storing performance monitoring data concerning performance monitoring events related to a pipelined microprocessor;
• determining that a particular performance monitoring event has occurred;
• analyzing the performance monitoring data on a processor cycle basis to locate a first performance monitoring data location associated with an instruction that was retiring from the pipeline in the pipelined microprocessor when the particular performance monitoring event occurred;
• and
• analyzing the performance monitoring data relative to the first performance monitoring data location on a retirement event basis to locate a second performance monitoring data location associated with an instruction that was executing at an identified pipeline stage in the pipelined microprocessor when the particular performance monitoring event occurred.

A method, comprising:

• storing performance monitoring data concerning performance monitoring events related to a pipelined microprocessor, where the performance monitoring data includes one or more of, pipeline stage data, instruction pointer data, cycle count data, instruction pointer validity data, pipeline flush status data, and data store freeze status data;
• determining that a particular performance monitoring event has occurred by receiving a signal that an event counter has reached a pre-determined count, where the particular performance monitoring event comprises one of, an instruction cache miss, a data cache miss, an instruction retirement, and a pipeline recirculate event;
• analyzing the performance monitoring data on a processor cycle basis to locate a first performance monitoring data location associated with an instruction that was retiring from the pipeline in the pipelined microprocessor when the particular performance monitoring event occurred, where analyzing the performance monitoring data on a processor cycle basis includes:
• identifying the last performance monitoring data that was stored;
• accessing a data value that stores a count of processor cycles that occurred between the last performance monitoring data being stored and the particular performance monitoring event occurring;
• starting from the last performance monitoring data stored, moving logically backwards in time through the performance monitoring data until an amount of performance monitoring data sufficient to account for the count of processor cycles has been traversed;
• and
• establishing the location in the performance monitoring data as the first performance monitoring data location;
• and
• analyzing the performance monitoring data relative to the first performance monitoring data location on a retirement event basis to locate a second performance monitoring data location associated with an instruction that was executing at an identified pipeline stage in the pipelined microprocessor when the particular performance monitoring event occurred, where analyzing the performance monitoring data relative to the first performance monitoring data location on a retirement event basis includes:
• accessing a data value that stores a count of the number of retirement events that occurred between the last performance monitoring data being stored and the particular performance monitoring event occurring;
• accessing a data value that identifies a pipeline stage with which the particular performance monitoring event is related;
• starting at the first performance monitoring data location, moving logically forwards in time through the performance monitoring data until an amount of performance monitoring data sufficient to account for the number of retirement events is traversed;
• and
• establishing the location as the second performance monitoring data location.

A computer-readable medium storing processor executable instructions operable to perform a method, the method comprising:

• analyzing monitoring data concerning performance monitoring events related to a pipelined microprocessor;
• determining that a particular performance monitoring event has occurred;
• moving through the performance monitoring data on a processor cycle basis to locate a first performance monitoring data location associated with an instruction that was retiring from the pipeline in the pipelined microprocessor when the particular performance monitoring event occurred;
• analyzing the performance monitoring data relative to the first performance monitoring data location on a retirement event basis to locate a second performance monitoring data location associated with an instruction that was executing at an identified pipeline stage in the pipelined microprocessor when the particular performance monitoring event occurred;
• and
• retrieving an address of an instruction associated with the particular performance monitoring event from the second performance monitoring data location.

A system for acquiring instruction addresses associated with performance monitoring events, comprising:

• means for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor;
• means for traversing the instruction and state data on a cycle count basis;
• and
• means for traversing the instruction and state data on a retirement count basis.

A data packet for transmitting performance monitoring data, comprising:

• a first field that stores an instruction pointer data configured to identify an instruction executing in a pipeline when a performance monitoring event occurred;
• a second field that stores a cycle count data configured to store a count of the number of processor cycles that occurred between two successive writes to a data store, where one of the writes included the instruction pointer data of the first field;
• a third field that stores an instruction pointer validity data configured to identify whether the instruction identified by the instruction pointer data in the first field was retired from the pipeline;
• a fourth field that stores a flush status data configured to identify whether the pipeline was flushed prior to retirement data being recorded for the instruction identified by the instruction pointer data in the first field;
• and
• a fifth field that stores a freeze status data configured to identify whether recording of performance monitoring data was suspended before retirement data was recorded for the instruction identified by the instruction pointer data in the first field.

A computer-readable medium having stored thereon a data structure comprising:

• a first field configured to store data representing the address of an instruction executing in a pipeline when a performance monitoring event occurred;
• a second field configured to store data representing a count of the number of processor cycles that occurred between two successive writes to a data store, where one of the writes included the address data in the first field;
• a third field configured to store data representing instruction pointer validity that identifies whether the instruction identified by the address in the first field was retired from the pipeline;
• a fourth field configured to store data representing a flush status that identifies whether the pipeline was flushed prior to retirement data being recorded for the instruction identified by the address in the first field;
• and
• a fifth field configured to store data representing a freeze status that identifies whether recording of performance monitoring data was suspended before retirement data was recorded for the instruction identified by the address in the first field.

A set of application programming interfaces embodied on a computer-readable medium for execution by a computer component in conjunction with locating addresses associated with instructions causing performance monitoring events, comprising:

• a first interface for communicating instruction pointer data;
• a second interface for communicating performance monitor event count data;
• and
• a third interface for communicating instruction pointer validity status data.

A method, comprising:

• recording instruction and state data for instructions as they retire from a pipeline in a pipelined microprocessor;
• counting an event caused by an instruction executing at a pipestage in the pipelined microprocessor;
• and
• determining whether the event is an event for which instruction and state data is to be collected, and, upon determining that the event is an event for which instruction and state data is to be recorded:
• selectively collecting address data associated with an instruction retiring from the pipeline;
• selectively collecting cycle count data concerning the number of cycles since a previous address data was collected;
• selectively collecting an instruction pointer validity data that identifies whether an instruction for which address data was collected successfully retired from a pipeline in the pipelined microprocessor;
• selectively collecting a flush status data that identifies whether the pipeline was flushed prior to retirement data being recorded for the instruction identified by the address data;
• and
• selectively collecting a freeze status data that identifies whether recording of performance monitoring data was suspended before retirement data was recorded for the instruction identified by the address data.