Combination of forwarding/bypass network with history file

A method, in a data processing system, for recovering the correct state of processor instructions, containing a pipeline of latches, a register file, and a replay loop, comprising:

• staging data results down the pipeline;
• detecting incorrect data results within the pipeline;
• committing the incorrect data results to the register file;
• sending the incorrect data results to the replay loop;
• repairing the incorrect data results by the replay loop;
• transmitting the repaired data results back into the pipeline;
• staging the repaired data results down the pipeline;
• committing the repaired data results to the register file to replace the incorrect data results;
• and
• forwarding the repaired data results.

A processor, comprising:

• a pipeline of latches that are at least configured to receive, store, and transmit data results;
• a memory controller that is at least configured to detect an incorrect result within the pipeline of latches and provide a correct result for the incorrect result;
• a register file coupled to the pipeline of latches, that is at least configured to store data results;
• a replay loop coupled to the pipeline of latches, containing a correction module;
• and
• a state machine, which includes logic for performing the following operations:
• controlling the correction module to repair incorrect results, and subsequently transmit the repaired results;
• and
• inserting the repaired results into the pipeline of latches.