Branch tracing generator device for a microprocessor and microprocessor equipped with such a device

A microcontroller, comprising:

• a device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type, said device including:
• means for receiving a first signal representative of an actually executed instruction;
• means for receiving a second signal representative of an expanded instruction;
• means for receiving a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by said microcontroller, microprocessor or data processing unit;
• means for storing consecutive addresses pointed by a program counter;
• means for processing said first, second and third signals in order to determine an address pair comprised of a source address and a destination address for an address branch, when appropriate;
• and
• means for storing said address pair.

A method to generate an address branch trace for a processor having a set of instructions including at least one predicated instruction and at least one instruction of an expanded type, the method comprising:

• receiving a first signal representative of an executed instruction;
• receiving a second signal representative of an expanded instruction;
• receiving a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by the processor;
• processing the first, second and third signals to determine a source address and a destination address for an address branch;
• and
• storing the determined source and destination addresses.

An apparatus to generate an address branch trace for a processor having a set of instructions including at least one predicated instruction and at least one instruction of an expanded type, the apparatus comprising:

• a first block to receive a first signal representative of an executed instruction;
• a second block to receive a second signal representative of an expanded instruction;
• a third block to receive a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by the processor;
• a fourth block coupled to the first, second, and third blocks to respectively process the first, second and third signals to determine an address pair for an address branch;
• and
• a storage unit coupled to the fourth block and to at least one of the first, second, or third blocks to store the determined address pair.