Vector processing system
AssigneeBroadcom Corporation
InventorsStephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
Life of this patent
Estimating the term…
Abstract
A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
Claims17
1-20. (canceled)
A vector processing system comprising:
- a circuit for receiving an instruction identifying a plurality of operands and specifying an operation;
- a plurality of parallel processing units, each arranged to generate a result according to the operation on one or more operands in the plurality of operands;
- and
- a scalar processing unit for generating a composite result according to the results from a selected number of parallel processing units.
A method for vector processing comprising:
- identifying a plurality of operands;
- specifying an operation;
- selecting the number of parallel executions of the operation;
- executing the operation in parallel on one or more operands in the plurality of operands to generate a plurality of results;
- and
- generating a composite result according to the plurality of results.
An integrated circuit for vector processing, wherein the integrated circuit comprises:
- a memory having stored thereon a computer program comprising an instruction stream including a vector instruction, the vector instruction defining
- multiple value pairs,
- an operation to be executed on each value pair, and
- a modifier;
- and
- a vector processing unit which comprises a plurality of parallel processing units, wherein each parallel processing unit is arranged to receive one of said value pairs and to selectively implement said operation, and wherein a processing unit is selected to operate on the basis of a condition defined by at least one flag in the processing unit, and wherein the condition is set by the modifier in the vector instruction, and wherein more than one results-from the plurality of parallel processing units is processed to generate a scalar result.
Dependencies are inferred from the claim text.