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OwnerJonathan DeMent, Kurt Feiste +3inventors
InventorsJonathan DeMent, Kurt Feiste, David Ray, David Shippy, Albert Van Norstrand
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A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could complete. The execution unit then takes over stalling until the non-pipelined instruction is actually completed. This allows the execution unit more time to accurately determine when the non-pipelined instruction will complete. Slightly before the execution unit has completed the instruction, it releases the stall to the issue logic. The timing of the execution unit releasing the stall signal is set so that a dependent instruction can bypass the result as soon as possible. In other words, the dependent instruction does not have to wait for the result to be written to the processor register file in order to obtain access to the result.
A method, in a data processing system, for handling non-pipelined instructions, comprising:
A processor, comprising:
A computer program product in a computer readable medium for handling non-pipelined instructions, comprising:
Dependencies are inferred from the claim text.