Mixed superscalar and VLIW instruction issuing and processing method and system

An integrated circuit forming a portion of a digital signal processor for encoding and processing instructions of mixed lengths, the integrated circuit comprising:

• an instruction unit for receiving in a mixed instruction listing a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions mixed among a plurality of series executable instructions, said series executable instructions associated by various instruction dependencies;
• a decode circuit for identifying in said mixed instruction listing said plurality of parallel executable instructions;
• a control circuit for executing in parallel said parallel executable instructions irrespective of the relative order of said parallel executable instructions in said mixed instruction listing;
• and
• said control circuit further for executing serially said series executable instructions according to said various instruction dependencies.

A digital signal processor for encoding and processing instructions of mixed lengths, the digital signal processor comprising:

• means for receiving in a mixed instruction listing a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions mixed among a plurality of series executable instructions, said series executable instructions associated by various instruction dependencies;
• means for identifying in said mixed instruction listing said plurality of parallel executable instructions;
• means for executing in parallel said parallel executable instructions irrespective of the relative order of said parallel executable instructions in said mixed instruction listing;
• and
• means for executing serially said series executable instructions according to said various instruction dependencies.

A computer usable medium having computer readable program code means embodied therein for operation in association with a digital signal processor for encoding and processing instructions of mixed lengths, the computer usable medium comprising:

• computer readable program code means for receiving in a mixed instruction listing a plurality of digital signal processor instructions, said plurality of digital signal processor instructions comprising a plurality of parallel executable instructions mixed among a plurality of series executable instructions, said series executable instructions associated by various instruction dependencies;
• computer readable program code means for identifying in said mixed instruction listing said plurality of parallel executable instructions;
• computer readable program code means for executing in parallel said parallel executable instructions irrespective of the relative order of said parallel executable instructions in said mixed instruction listing;
• and
• computer readable program code means for executing serially said series executable instructions according to said various instruction dependencies.