Method and apparatus for reducing system inactivity during time data float delay and external memory write

A method for reducing inactive periods in an integrated circuit coupled to an external peripheral by an external data bus, the integrated circuit having a processor, an address decoder coupled to the processor by an internal data bus, an external bus circuit coupled to the internal data bus and the external data bus, the method comprising:

• receiving a read signal for data from the external peripheral;
• generating a wait signal until data from the external peripheral is available on the internal data bus, wherein the wait signal indicates that the external and internal data busses are not available for other purposes;
• reading data from the external peripheral through the internal data bus;
• stopping generation of the wait signal;
• and
• generating a busy signal, the busy signal indicating that the internal data bus is available and the external data bus is not available for other purposes.

A method for reducing inactive periods in a integrated circuit coupled to an external peripheral by an external data bus, the integrated circuit having a processor, an address decoder coupled to the processor by an internal data bus, an external bus circuit coupled to the internal data bus and the external data bus, the method comprising:

• receiving a write signal for the external peripheral;
• generating a wait signal until data is available on the external bus circuit, the wait signal indicating that the internal data bus is and the external bus circuit are not available;
• generating a busy signal until the external peripheral is available on the external data bus, the busy signal indicating that the internal data bus is available and the external data bus is not available for other purposes;
• writing to the external peripheral through the external data bus;
• and
• stopping generation of the busy signal.