Memory interface architecture for maximizing access timing margin
AssigneeLSI Logic Corporation
InventorsHui-Yin Seto, Cheng-Gang Kong
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Abstract
An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.
Claims20
An apparatus comprising:
- a control circuit configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate, wherein a second signal in each of said pairs comprises a clock signal operating at said second data rate;
- a buffer circuit configured to generate a buffered signal in response to each of said pairs of signals, wherein each of said buffered signals operates at said second data rate;
- and
- a memory circuit configured to read and write data at said second data rate in response to said buffered signals.
An apparatus comprising:
- means for presenting a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate, wherein a second signal in each of said pairs comprises a clock signal operating at said second data rate;
- means for generating a buffered signal in response to each of said pairs of signals, wherein each of said buffered signals operates at said second data rate;
- and
- a memory configured to read and write data at said second data rate in response to said buffered signals.
A method for reading and writing data comprising the steps of:
- (A) presenting a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate, wherein a second signal in each of said pairs comprises a clock signal operating at said second data rate;
- (B) generating a buffered signal in response to each of said pairs of signals, wherein each of said buffered signals operates at said second data rate;
- and
- (C) reading and writing data at said second data rate in response to said buffered signals.
Dependencies are inferred from the claim text.