# US 2006/0224837 A1 · Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2006/0224837 A1 - Document ID: US20060224837A1 - Status: Published application - Kind: A1 - Application number: 11/093,131 - Filed: 2005-03-29 - Published: 2006-10-05 - Earliest claimed: 2005-03-29 - Assignees: International Business Machines Corporation - Inventors: Matthias Blumrich; Dong Chen; Alan Gara; Mark Giampapa; Philip Heidelberger; Dirk Hoenicke; Martin Ohmacht; Valentina Salapura; Pavlos Vranas - Web page: https://patentgrep.com/patent/US20060224837A1 ## CPC - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/084: with a shared cache - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit. ## Claims ### Claim 1 A system for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated therewith and operatively connected via a first communications means, said system comprising: a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in said multiprocessor computing environment; a point-to-point interconnect means comprising communication links for directly connecting said memory writing sources to the dedicated input ports of all other snoop filter devices associated with all other processing devices of said multiprocessor computing environment; each said snoop filter device further having a plurality of parallel operating port snoop filters in correspondence with said plurality of dedicated input ports, said plurality of port snoop filters adapted to concurrently filter snoop requests received from respective said dedicated memory writing sources and forward a subset of those requests to its associated processing unit, whereby a number of snoop requests forwarded to a processing unit is significantly reduced thereby increasing performance of said computing environment. ### Claim 2 (depends on 1) The system as claimed in claim 1, wherein a dedicated memory writing source of said snoop request comprises one of said multiple processing units. ### Claim 3 (depends on 1) The system as claimed in claim 1, wherein a dedicated memory writing source of said snoop request comprises a Direct Memory Access (DMA) engine. ### Claim 4 (depends on 1) The system as claimed in claim 1, wherein each said snoop filter device further comprises: a plurality of processor snoop filter queue means in correspondence with said plurality of port snoop filters for receiving, enqueing, and forwarding said subset of snoop requests to the associated processor unit of said snoop filter device. ### Claim 5 (depends on 4) The system as claimed in claim 4, wherein each said snoop filter device further comprises: means for arbitrating between all of the snoop filter queue means and serializing all snoop requests forwarded from each of said plurality of processor snoop filter queue means for forwarding to said associated processor unit. ### Claim 6 (depends on 4) The system as claimed in claim 4, further comprising means for preventing a queue overflow condition in each said processor snoop filter queue means, said means comprising: for each snoop filter device: a means for issuing a token to each memory writing source via its dedicated point-to-point communication link indicating availability to receive a snoop request at that port; and, means for collecting tokens at said memory writing source, wherein a snoop request corresponding to a memory write from said memory writing source is transmitted to each said snoop filter device when at least one token is available for each snoop filter device for which it is directly point-to-point connected. ### Claim 7 (depends on 1) The system as claimed in claim 1, wherein each port snoop filter of said plurality of port snoop filters comprises one or more sub-filter elements for filtering out received snoop requests. ### Claim 8 (depends on 1) The system as claimed in claim 1, wherein said one or more local cache memories associated with a processing unit comprises first and second cache memory levels, said associated snoop filter device adapted for filtering out snoop requests at said first cache memory level. ### Claim 9 (depends on 1) The system as claimed in claim 1, wherein said one or more local cache memories associated with a processing unit comprises first and second cache memory levels, said associated snoop filter device adapted for filtering out snoop requests at said second cache memory level. ### Claim 10 A method for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated therewith and operatively connected via a first communications means, said method comprising: providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in said multiprocessor computing environment; directly connecting each said memory writing source to the dedicated input ports of all other snoop filter devices associated with all other processing devices of said multiprocessor computing environment in a point-to-point interconnect fashion; providing, for each said snoop filter device, a plurality of parallel operating port snoop filters in correspondence with said plurality of dedicated input ports, each said plurality of port snoop filters adapted to concurrently filter snoop requests received from respective said dedicated memory writing sources and forward a subset of those requests to its associated processing unit, whereby a number of snoop requests forwarded to a processing unit is significantly reduced thereby increasing performance of said computing environment. ### Claim 11 (depends on 10) The method for supporting cache coherency as claimed in claim 10, wherein a dedicated memory writing source of said snoop request comprises one of said multiple processing units. ### Claim 12 (depends on 10) The method for supporting cache coherency as claimed in claim 10, wherein a dedicated memory writing source of said snoop request comprises a Direct Memory Access (DMA) engine. ### Claim 13 (depends on 10) The method for supporting cache coherency as claimed in claim 10, further comprising the step of: providing a plurality of processor snoop filter queue means in correspondence with said plurality of port snoop filters, each respective processor snoop filter queue means for receiving, enqueing, and forwarding said subset of snoop requests to the associated processor unit of said snoop filter device. ### Claim 14 (depends on 13) The method for supporting cache coherency as claimed in claim 13, further comprising the steps of: arbitrating between all of the snoop filter queue means and serializing all snoop requests forwarded from each of said plurality of processor snoop filter queue means for forwarding to said associated processor unit. ### Claim 15 (depends on 13) The method for supporting cache coherency as claimed in claim 13, further comprising the step of: preventing a queue overflow condition in each said processor snoop filter queue means, said preventing step comprising: for each snoop filter device: issuing a token to each memory writing source via its dedicated point-to-point communication link indicating availability to receive a snoop request at that port; collecting tokens at said memory writing source; and, transmitting a snoop request corresponding to a memory write from said memory writing source to each said snoop filter device when at least one token is available for each snoop filter device for which it is directly point-to-point connected. ### Claim 16 (depends on 10) The method for supporting cache coherency as claimed in claim 10, wherein each port snoop filter of said plurality of port snoop filters comprises one or more sub-filter elements for filtering out received snoop requests. ### Claim 17 (depends on 10) The method for supporting cache coherency as claimed in claim 10, wherein said one or more local cache memories associated with a processing unit comprises first and second cache memory levels, said associated snoop filter device adapted for filtering out snoop requests at said first cache memory level. ### Claim 18 (depends on 10) The method for supporting cache coherency as claimed in claim 10, wherein said one or more local cache memories associated with a processing unit comprises first and second cache memory levels, said associated snoop filter device adapted for filtering out snoop requests at said second cache memory level.