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US 2006/0224834 A1Published application
Write-back cache methods and apparatus
AssigneeIntel Corporation
InventorsDennis O'Connor, Michael Morrow
Life of this patent
Estimating the term…
Abstract
A cache controller prevents the use of data in a write-back cache memory from being propagated until the data is backed-up in a main memory. Control bits inhibit portions of the cache memory from being accessed.
Claims30
A cache comprising:
- access logic responsive to an access request;
- a cache memory coupled to the access logic, wherein a portion of the cache memory comprises at least one no-touch bit;
- and
- the at least one no-touch bit to control access to the portion of the cache memory in response to the access request.
1 more element
A semiconductor device comprising:
- a cache controller including a cache memory, the cache controller coupled to a processor;
- and
- the cache memory including a plurality of no-touch bits, each of the plurality of no-touch bits to inhibit access to or modification of a portion of the cache memory by the processor.
A system comprising:
- at least one non-processor client to request access to a cache memory;
- a core including the cache memory, the core coupled to the at least one non-processor client;
- and
- the cache memory including a plurality of no-touch bits, each of the plurality of no-touch bits to inhibit access to or modification of a portion of the cache memory by the core in response to an access request by the at least one non-processor client.
1 more element
A method comprising:
- setting by a cache memory at least one of a plurality of no-touch bits corresponding to an address from an access request by a client;
- and
- if any of the plurality of no-touch bits corresponding to the address is set, indicating that the address is not found in the cache memory.
Dependencies are inferred from the claim text.