Semiconductor memory devices having controllable input/output bit architectures and related methods

A method of forming a semiconductor memory device, the method comprising:

• forming a plurality of unit memory devices on a semiconductor wafer wherein each of the unit memory devices includes a respective command signal pad, a respective address signal pad, and a respective clock signal pad;
• forming a command signal line electrically coupling a first command signal pad and a second command signal pad of a respective first unit memory device and a second unit memory devices of the plurality of memory devices;
• forming an address signal line electrically coupling a first address signal pad and a second address signal pad of the respective first and second unit memory devices;
• forming a clock signal line electrically coupling a first clock signal pad and a second clock signal pad of the respective first unit memory device and the second unit memory device;
• and
• cutting the semiconductor wafer to separate at least a third unit memory device of the plurality of unit memory devices from the first unit memory device and the second unit memory device while maintaining the first unit memory device and the second unit memory device on a same semiconductor substrate cut from the semiconductor wafer.