Multi CPU system
AssigneeCanon Kabushiki Kaisha
InventorKatsunari Suzuki
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Abstract
A multi CPU system is capable of performing exclusive control of a plurality of CPUs accessing to the same resource by a hardware without depending on an OS. The plurality of CPUs are connected with the same system bus. A plurality of circuits one-to-one correspond to each of the plurality of CPUs and comprise respective semaphore acquisition registers. Each of the CPUs in accessing to the resource is controlled, based on the value written in the semaphore acquisition register of the corresponding circuit, the presence or absence of the priority in the semaphore control, and a semaphore signal received from the another circuit.
Claims9
A multi CPU system in which a plurality of CPUs are connected with the same system bus, comprising a plurality of circuits which one-to-one correspond to each of said plurality of CPUs,
- wherein each of said plurality of circuits comprises:
- a semaphore acquisition register in which a value indicating a write access is written when a corresponding CPU performs the write access to a resource on said system bus;
- a semaphore controlling unit that outputs a semaphore signal indicating that the corresponding CPU performs a write access based on the value written in said semaphore acquisition register and receives a semaphore signal from another circuit, to thereby perform semaphore control of the corresponding CPU;
- and
- a semaphore priority decision unit that determines the presence or absence of priority in the semaphore control to the corresponding CPU,
- wherein said semaphore controlling unit that controls the corresponding CPU in accessing to said resource, based on the value written in said semaphore acquisition register, the presence or absence of the priority in said determined semaphore control, and the semaphore signal received from said another circuit.
Dependencies are inferred from the claim text.