Mechanism for a shared serial peripheral interface
AssigneeIntel Corporation
InventorsAmir Zinaty, Adit Tarmaster, Michael Derr, Haim Lustig
Life of this patent
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Abstract
According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.
Claims20
A chipset comprising an arbiter coupled to a serial peripheral interface (SPI) and a master device to arbitrate between the chipset and the master device for control of the SPI to access a slave device.
A computer system comprising:
- a flash memory device;
- a serial peripheral interface (SPI) coupled to the flash memory device;
- a network controller coupled to the SPI;
- and
- a chipset, coupled to the SPI, having an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.
A method comprising:
- receiving a request from a first master device to control a serial peripheral interface (SPI) to access a slave device;
- and
- receiving a second request from a second master device to control the SPI to access the slave device.
Dependencies are inferred from the claim text.