Method and apparatus for concurrent and independent data transfer on host controllers
AssigneeIntel Corporation
InventorEng Ooi
Life of this patent
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Abstract
An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.
Claims20
An apparatus comprising:
- a first host controller interfacing to a first hard drive, wherein for a first data transfer operation, a device bit in a device/head register on the first host controller is written to before other registers on the first host controller;
- and
- wherein based on the data written in the device/head register on the first host controller, transfer data is written to another register on the first host controller.
An apparatus comprising:
- a plurality of parallel channels;
- a plurality of serial ports interfacing to serial storage devices, wherein the parallel channels are mapped to serial ports;
- a device/head register on a first serial port, wherein for a first data transfer operation, the device/head register is written to before other registers on the first serial port;
- and
- wherein based on the data written in the device/head register of the first serial port, another register on the first serial port is accessed.
The apparatus of claim 14, wherein writing to a device/head register on a first serial port before writing to other registers on the first serial port comprises writing to the device bit in the device/head register before writing to a bus master or task file register of the first serial port.
A system comprising:
- a plurality of serial storage devices;
- and
- a chipset coupled to the serial storage devices, the chipset having a serial storage controller, the serial storage controller comprising:
- a mapping circuit to map a plurality of serial ports interfacing to the serial storage devices to a plurality of parallel channels;
- a state machine coupled to the mapping circuit to emulate a response from the one of the parallel channels based on an access type;
- a serial port selector coupled to the state machine and the serial ports to select one of the serial ports;
- and
- a plurality of registers coupled to the state machine to emulate task file registers of the parallel channel mapped to the selected serial port, wherein a device bit in a device/head register of the selected serial port is written to before any one of a corresponding bus master or task file registers.
Dependencies are inferred from the claim text.