Instruction set processor enhancement for computing a fast fourier transform
AssigneeNokia Corporation
InventorsKim Rounioja, Sien Ong
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Abstract
This invention describes a method of computing a fast Fourier transform (FFT) using enhanced processor computational capabilities for more efficient and flexible implementation of an electronic device (e.g., a linear equalizer) based on that FFT computing. A simple non-parallel instruction set processor (or just a non-parallel processor) containing complex multiplication and addition/subtraction capabilities is extended by adding additional registers and interconnects and a dedicated parallel instruction for calculating the FFT butterfly. The parallel instruction consists of orthogonal sub-instructions each controlling a section of the data path related to a corresponding section of the FFT butterfly.
Claims27
A method for enhancing computational capabilities of a processor having complex multiplication and addition/subtraction capabilities for computing a fast Fourier transform, comprising the steps of:
- adding at least one further register and at least one further interconnect to said processor for performing FFT butterfly computing of said fast Fourier transform;
- and
- adding a parallel instruction to said processor utilizing said at least one further register and said at least one further interconnect for said computing of said FFT butterfly, thus enhancing said computational capabilities of said processor,
- wherein said processor is not dedicated to only said computing of said fast Fourier transform.
A processor, having complex multiplication and addition/subtraction capabilities and having enhanced computational capabilities for computing a fast Fourier transform, is characterized in that said enhanced computational capabilities comprise:
- at least one further register and at least one further interconnect, for performing FFT butterfly computing of said fast Fourier transform;
- and
- a parallel instruction utilizing said at least one further register and said at least one further interconnect for said computing of said FFT butterfly, thus enhancing said computational capabilities of said processor,
- wherein said processor is not dedicated to only said computing of said fast Fourier transform.
An electronic device having a processor containing complex multiplication and addition/subtraction capabilities and enhanced computational capabilities for computing a fast Fourier transform, is characterized in that said enhanced computational capabilities comprise:
- at least one further register and at least one further interconnect, for performing FFT butterfly computing of said fast Fourier transform;
- and
- a parallel instruction utilizing said at least one further register and said at least one further interconnect for said computing of said FFT butterfly, thus enhancing said computational capabilities of said processor,
- wherein said processor is not dedicated to only said computing of said fast Fourier transform.
Dependencies are inferred from the claim text.