System and method for reducing jitter of signals coupled through adjacent signal lines

A system for coupling first and second digital signals from a first location to a second location through first and second signal lines, respectively, the system comprising:

• a mode detector coupled to the first and second signal lines at the first location, the mode detector being operable to detect each transition of the first and second signals and determine a delay value for the first and second signals based on the detected transitions;
• a first delay circuit coupled to the mode detector, the first delay circuit coupling the first signal to the first signal line at the first location, the first delay circuit coupling the first signal to the first signal line with a delay corresponding to the delay value;
• and
• a second delay circuit coupled to the mode detector, the second delay circuit coupling the second signal to the second signal line at the first location, the second delay circuit coupling the first signal to the second signal line with a delay corresponding to the delay value so that the time at which the first and second signals propagate to a location in the signal lines is substantially insensitive to variations in the transitions of the first and second signals.

A system for coupling first and second digital signals from a first location to a second location through first and second signal lines, respectively, the system comprising:

• a first delay circuit coupling the first signal to the first signal line at the first location, the first delay circuit coupling the first signal to the first signal line with a delay corresponding to a delay value;
• a second delay circuit coupling the second signal to the second signal line at the first location, the second delay circuit coupling the second signal to the second signal line with a delay corresponding to a delay value;
• a pattern generator coupled to the first and second delay circuits and to the first signal line at the first location, the pattern generator applying first and second digital test signals to the first and second signal lines, respectively, over a range of discrete delay values, the first digital test signal being applied to the first signal line in a predetermined pattern over the range of discrete delay values;
• a pattern detector coupled to the first signal line at the second location, the pattern detector being operable to detect the predetermined pattern at the second location and to provide the feedback data indicative of whether the predetermined pattern is detected at each of the discrete delay values;
• and
• a mode detector coupled to the pattern generator and to the first and second signal lines at the first location, the mode detector being operable to select respective delay values for each of a plurality of relative transition characteristics of the first and second signals based on the feedback data from the pattern detector, the mode detector being operable to couple the selected delay values to the first and second delay circuits.

A system for coupling a plurality of digital signals from a first location to a second location, the system comprising:

• a plurality of signal lines corresponding in number to the number of digital signals being coupled from the first location to the second location, the signal lines being divided into a plurality of pairs, the signal lines in each pair being position substantially closer to each other than they are to any signal line in another pair;
• a plurality of mode detectors coupled to respective pairs of the signal lines at the first location, the mode detector being operable to detect each transition of the signals coupled to the signal lines in the respective pair and determine a respective delay value for at least one of the signals based on the detected transitions;
• a respective first delay circuit coupled to each of the mode detectors, each of the first delay circuits coupling one of the signals to one of the signal lines in the respective pair at the first location, each of the first delay circuits coupling the signal to the signal line with a delay corresponding to the delay value;
• and
• a respective second delay circuit coupled to each of the mode detectors, each of the second delay circuits coupling one of the signals to one of the signal lines in the respective pair at the first location, the second delay circuit coupling the signal to the signal line with a delay corresponding to the delay value so that the timing at which the signals coupled through each pair of signal lines propagate to a location in the signal lines is substantially insensitive to variations in the transitions of the signals.

A memory system, comprising:

• a memory controller;
• a memory device coupled to the memory controller through at least one pair of signal lines;
• a mode detector coupled to the signal lines at the memory controller, the mode detector being operable to detect each transition of signals coupled from the memory controller to the memory device through the signal lines and to determine a delay value for the signals based on the detected transitions;
• a first delay circuit coupled to the mode detector, the first delay circuit coupling one of the signals to a respective one of the signal lines at the memory controller, the first delay circuit coupling the signal to the signal line with a delay corresponding to the delay value;
• and
• a second delay circuit coupled to the mode detector, the second delay circuit coupling another one of the signals to a respective one of the signal lines at the memory controller, the second delay circuit coupling the signal to the signal line with a delay corresponding to the delay value so that the time at which the signals propagate to the memory device is substantially insensitive to variations in the transitions of the signals.

A memory system, comprising:

• a memory device;
• a memory controller coupled to the memory device through at least one pair of signal lines;
• a mode detector coupled to the signal lines at the memory device, the mode detector being operable to detect each transition of signals coupled from the memory device to the memory controller through the signal lines and to determine a delay value for the signals based on the detected transitions;
• a first delay circuit coupled to the mode detector, the first delay circuit coupling one of the signals to a respective one of the signal lines at the memory device, the first delay circuit coupling the signal to the signal line with a delay corresponding to the delay value;
• and
• a second delay circuit coupled to the mode detector, the second delay circuit coupling another one of the signals to a respective one of the signal lines at the memory device, the second delay circuit coupling the signal to the signal line with a delay corresponding to the delay value so that the time at which the signals propagate to the memory controller is substantially insensitive to variations in the transitions of the signals.

A memory system, comprising:

• a memory controller;
• a memory device;
• at least one bus coupling the memory controller to the memory device, the at least one bus having a plurality of signal lines divided into a plurality of pairs, the signal lines in each pair being position substantially closer to each other than they are to any signal line in another pair;
• a plurality of mode detectors coupled to respective pairs of the signal lines at the memory controller, the mode detectors being operable to detect each transition of the signals coupled to the signal lines in the respective pair and to determine a delay value for the signals based on the detected transitions;
• and
• a respective first delay circuit coupled to each of the mode detectors, each of the first delay circuits coupling one of the signals to one of the signal lines in the respective pair at the memory controller, the first delay circuit coupling the signal to the signal line with a delay corresponding to the delay value;
• a respective second delay circuit coupled to each of the mode detectors, each of the second delay circuits coupling another one of the signals to one of the signal lines in the respective pair at the memory controller, the second delay circuit coupling the signal to the signal line with a delay corresponding to the delay value so that the time at which the signals propagate to the memory device is substantially insensitive to variations in the transitions of the signals.

A memory system, comprising:

• a memory controller;
• a memory device;
• at least one bus coupling the memory controller to the memory device, the at least one bus having a plurality of signal lines divided into a plurality of pairs, the signal lines in each pair being position substantially closer to each other than they are to any signal line in another pair;
• a plurality of mode detectors coupled to respective pairs of the signal lines at the memory device, the mode detectors being operable to detect each transition of the signals coupled to the signal lines in the respective pair and to determine a delay value for the signals based on the detected transitions;
• and
• a respective first delay circuit coupled to each of the mode detectors, each of the first delay circuits coupling one of the signals to one of the signal lines in the respective pair at the memory device, the first delay circuit coupling the signal to the signal line with a delay corresponding to the delay value;
• a respective second delay circuit coupled to each of the mode detectors, each of the second delay circuits coupling another one of the signals to one of the signal lines in the respective pair at the memory device, the second delay circuit coupling the signal to the signal line with a delay corresponding to the delay value so that the time at which the signals propagate to the memory controller is substantially insensitive to variations in the transitions of the signals.

A processor-based system, comprising

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• a memory controller;
• a memory device coupled to the memory controller through at least one pair of signal lines;
• a mode detector coupled to the signal lines at the memory controller, the mode detector being operable to detect each transition of signals coupled from the memory controller to the memory device through the signal lines and to determine a delay value for the signals based on the detected transitions;
• a first delay circuit coupled to the mode detector, the first delay circuit coupling one of the signals to a respective one of the signal lines at the memory controller, the first delay circuit coupling the signal to the signal line with a delay corresponding to the delay value;
• and
• a second delay circuit coupled to the mode detector, the second delay circuit coupling another one of the signals to a respective one of the signal lines at the memory controller, the second delay circuit coupling the signal to the signal line with a delay corresponding to the delay value so that the time at which the signals propagate to the memory device is substantially insensitive to variations in the transitions of the signals.

A processor-based system, comprising

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• a memory controller;
• a memory device coupled to the memory controller through at least one pair of signal lines;
• a mode detector coupled to the signal lines at the memory device, the mode detector being operable to detect each transition of signals coupled from the memory device to the memory controller through the signal lines and to determine a delay value for the signals based on the detected transitions;
• a first delay circuit coupled to the mode detector, the first delay circuit coupling one of the signals to a respective one of the signal lines at the memory device, the first delay circuit coupling the signal to the signal line with a delay corresponding to the delay value;
• and
• a second delay circuit coupled to the mode detector, the second delay circuit coupling another one of the signals to a respective one of the signal lines at the memory device, the second delay circuit coupling the signal to the signal line with a delay corresponding to the delay value so that the time at which the signals propagate to the memory controller is substantially insensitive to variations in the transitions of the signals.