Self-aligned contacts for transistors

A method comprising:

• polishing a wafer that includes a gate, spacers adjacent to the gate, and a diffusion layer with drain and source regions, wherein the polishing stops at a top of the spacers;
• removing an upper portion of the gate so that a top of the gate is recessed with respect to the top of the spacers such that a gate recess is formed;
• filling the gate with a protective material;
• patterning an etch-resistant material to create an opening that resides (1) above the spacers, (2) above the protective material, and (3) above areas adjacent to the spacers;
• performing a selective etch through the opening that does not etch the gate, the protective material, or the spacers, but does etch material that resides laterally with respect to the spacers in order to expose tops, immediately adjacent to the spacers, of the drain and source regions of the diffusion layer;
• depositing conductive material that covers respective tops of the drain and source regions of the diffusion layer to a depth that does not short the drain and source regions of the diffusion layer;
• forming a layer above the conductive material;
• forming, in the layer above the conductive material, metal lines that contact respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer.

An apparatus comprising:

• a gate of a transistor;
• a first spacer adjacent to a first side of the gate;
• a second spacer adjacent to a second side of the gate;
• a diffusion layer of the transistor, wherein the diffusion layer includes a source region and a drain region;
• a first conductive region adjacent to the first spacer, wherein the first conductive region is superadjacent to and contacts the source region of the diffusion layer of the transistor, wherein the first conductive region is planarized with respect to a top of the first spacer;
• a second conductive region adjacent to the second spacer, wherein the second conductive region is superadjacent to and contacts the drain region of the diffusion layer of the transistor, wherein the second conductive region is planarized with respect to a top of the second spacer;
• a first contact residing in a first via above the first conductive region and contacting the first conductive region;
• a second contact residing in a second via above the second conductive region and contacting the second conductive region.