Non-critical complementary masking method for poly-1 definition in flash memory device fabrication
AssigneeSpansion LLC
InventorsUnsoon Kim, Hiroyuki Kinoshita, Yu Sun, Krishnashree Achuthan, Christopher Raeder, Christopher Foster, Harpreet Sachar, Kashmir Sahota
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Abstract
A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
Claims16
A method of defining a poly-1 layer of a chip on a semiconductor wafer, said chip comprising a core memory area and a peripheral region, comprising:
- creating mesas of oxide material protruding from a substrate in said core memory area;
- depositing a poly-1 layer over said substrate and tall mesas of oxide material in the core memory area;
- creating a non-critical mask over said peripheral region, leaving said core memory are exposed,
- polishing said semiconductor wafer to expose tops of said tall oxide mesas in said core memory area,
- removing said non-critical mask.
A method of defining a poly-1 layer of a semiconductor chip, said semiconductor chip comprising a core memory area and a peripheral region, comprising:
- depositing a thick nitride barrier level above a substrate of said semiconductor chip;
- etching shallow isolation trenches into said nitride layer and said substrate;
- filling said shallow isolation trenches with oxide material;
- removing excess of said oxide material from on top of remainder of said nitride layer;
- depositing a first non-critical mask on said core memory area, leaving said peripheral region exposed;
- recessing said oxide material in said exposed peripheral region by an amount approximately equal to a final polysilicon thickness;
- stripping said first non-critical mask;
- stripping a remainder of said nitride barrier layer, thereby leaving mesas of oxide material in said core memory area;
- depositing a layer of polysilicon, called the poly-1 layer, over said core memory area and said peripheral region;
- depositing a thin hard mask over said core memory area and said peripheral region;
- depositing a second non-critical complimentary mask over said peripheral region;
- etching away an exposed portion of said thin hard mask over said core memory area;
- polishing an exposed core memory area to remove said polysilicon from on top of said mesas of field oxide in said core memory area;
- stripping said complimentary mask;
- stripping a remaining portion of said thin hard mask.
Dependencies are inferred from the claim text.