US 2006/0223269 A1Published application

Method of manufacturing semiconductor device

AssigneeOki Electric Industry Co., Ltd.

InventorToshihiro HONMA

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Abstract

A method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having first to fourth active regions and field oxides, the third and fourth active regions sandwiching the second active region, and the field oxides isolating the first to fourth active regions; forming a protective film having openings over the second active region and the field oxide which adjoins the second active region, over the semiconductor substrate; forming the first gate insulator on the second active region; removing the protective film; forming second gate insulators thinner than the first gate insulators on the first, third and fourth active regions, respectively; forming gate electrodes on the first gate insulator over the first active region and on the second gate insulator over the second active region; and forming a pair of first doped regions in the first active region and second doped regions in the third and fourth active regions.

Claims8

Dependent claims

A method of manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate having first to fourth active regions and element isolating insulation films, the third and fourth active regions sandwiching the second active region, and the element isolating insulation films isolating the first to fourth active regions, respectively;
forming a protective film for preventing the semiconductor substrate from being oxidized, the protective film having openings over the second active region and the element isolating insulation film adjoining the second active region;
forming the first gate insulation film on the second active region by conducting a thermal oxidation treatment on the semiconductor substrate exposed at the openings;
removing the protective film;
forming second gate insulation films on the first, third and fourth active regions, respectively, by conducting a thermal oxidation treatment, the second gate insulation films being thinner than the first gate insulation film;
forming gate electrodes on the first gate insulation film over the first active region and on the second gate insulation film over the second active region, respectively;
and
forming a pair of first doped regions in the first active region and second doped regions in the third and fourth active regions.

5 more elements

A method of manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate having first to fourth active regions and element isolating insulation films, the third and fourth active regions sandwiching the second active region, and the element isolating insulation films isolating the first to fourth active regions, respectively;
forming a protective film for preventing the semiconductor substrate from being oxidized, the protective film having openings over the second active region and the element isolating insulation film adjoining at least one of the second to fourth active regions;
forming the first gate insulation film on the second active region by conducting a thermal oxidation treatment on the semiconductor substrate exposed at the openings;
removing the protective film;
forming second gate insulation films on the first, third and fourth active regions, respectively, by conducting a thermal oxidation treatment, the second gate insulation films being thinner than the first gate insulation film;
forming gate electrodes on the first gate insulation film over the first active region and on the second gate insulation film over the second active region, respectively;
and
forming a pair of first doped regions in the first active region and second doped regions in the third and fourth active regions.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/276,826Filed 15 Mar 2006
Priority: JP 2005/09437329 Mar 2005
Published: 5 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 84/859
Complementary IGFETs, e.g. CMOS: comprising both N-type and P-type wells, e.g. twin-tub
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0181
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate insulating layers
H10D 84/0191
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells