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US 2006/0223250 A1Published application
Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning
AssigneeAdvanced Micro Devices, Inc.
InventorsKarla Romero, Thorsten Kammler, Scott Luning, Hans Van Meer
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Abstract
By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.
Claims28
A method, comprising:
- forming a layer of gate electrode material above a semiconductor region;
- forming a hard mask layer stack on said layer of gate electrode material, said hard mask layer stack comprising a first layer next to said layer of gate electrode material, a second layer next to said first layer and a third layer next to said second layer;
- patterning said hard mask layer stack to form an etch mask comprised of at least said first layer;
- patterning said layer of gate electrode material by means of said etch mask to form a gate electrode;
- and
- selectively epitaxially growing a semiconductor material on said semiconductor region while a top surface of said gate electrode is covered by at least said first layer.
3 more elements
A method, comprising:
- determining in advance a first target thickness, a second target thickness and a third target thickness for a first layer, a second layer and a third layer, respectively, of a hard mask layer stack;
- forming a layer of gate electrode material above a semiconductor region of a substrate;
- forming said hard mask layer stack on said layer of gate electrode material formed on said substrate;
- patterning said layer of gate electrode material by means of said hard mask layer stack to form a gate electrode;
- and
- selectively epitaxially growing a semiconductor material on said semiconductor region of said substrate while a top surface of said gate electrode is covered by said first layer.
3 more elements
Dependencies are inferred from the claim text.