N+ poly on high-k dielectric for semiconductor devices
AssigneeTexas Instruments Incorporated
InventorsRamesh Venugopal, Christoph Wasshuber, David Scott
Life of this patent
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Abstract
The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
Claims21
A method of fabricating a PMOS transistor device comprising:
- forming a n-type well region within a semiconductor body;
- performing a threshold voltage adjustment implant by implanting a p-type dopant into the n-type well region to form a shallow counter doped region;
- forming a high-k dielectric layer over the device;
- forming a polysilicon layer on the high-k dielectric layer;
- patterning the high-k dielectric layer and the polysilicon layer to form a polysilicon gate structure;
- implanting a p-type dopant into active areas of the n-type well region to form source/drain regions;
- and
- implanting an n-type dopant into the polysilicon layer to form an n-type doped polysilicon gate structure.
A method of fabricating a semiconductor device comprising:
- forming isolation regions;
- forming n-type well regions in a PMOS region of a semiconductor body;
- forming p-type well regions in an NMOS region of the semiconductor body;
- performing a threshold voltage adjustment implant within the NMOS region by implanting a p-type dopant;
- performing a threshold voltage adjustment implant within the PMOS region by implanting a p-type dopant;
- forming a high-k dielectric layer over the device;
- forming a polysilicon gate layer on the high-k dielectric layer;
- patterning the high-k dielectric layer and the poly gate layer to form polysilicon gate structures within the PMOS region and the NMOS region;
- forming a PSD resist mask that exposes active areas of the PMOS region and covers the NMOS region and the gate structures of the PMOS region;
- forming source/drain regions in active areas of the PMOS region by implanting a p-type dopant;
- removing the PSD resist mask;
- forming an NSD resist mask that exposes the NMOS region and the gate structures of the PMOS region and covers the active areas of the PMOS region;
- forming source/drain regions in active areas of the NMOS region and n-type doped polysilicon gate structures of the NMOS region and the PMOS region by implanting an n-type dopant;
- and
- removing the NSD resist mask.
A semiconductor device comprising:
- an n-type well region formed within a semiconductor body;
- a shallow p-type counter doped region formed within the n-type well region;
- a polysilicon gate structure formed on the n-type well region comprised of an n-type doped polysilicon gate formed on a high-k dielectric layer;
- and
- p-type source and drain regions formed within the n-type well region on opposite sides of the polysilicon gate structure.
Dependencies are inferred from the claim text.