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US 2006/0223211 A1Published application
Semiconductor devices based on coalesced nano-rod arrays
AssigneeThe Regents of the University of California
InventorsUmesh Mishra, Stacia Keller
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Abstract
Semiconductor devices are fabricated using semiconductor nano-rod arrays, which are merged through coalescence into a continuous planar layer after the nano-rods in the nano-rod array are fabricated by growth or etching. Merging of the nano-rods through coalescence into a continuous layer is achieved by tuning the growth conditions into a regime allowing epitaxial lateral overgrowth.
Claims21
A method of fabricating a semiconductor device, comprising:
- merging semiconductor nano-rods in a nano-rod array through coalescence into a continuous planar layer after fabrication of the nano-rods.
A method of fabricating a semiconductor device, comprising:
- (a) depositing a conducting (Al,Ga)N nucleation layer on a substrate in a growth chamber, followed by the deposition of a n-type GaN:Si layer;
- (b) removing the substrate from the growth chamber and depositing a SiO2 layer onto the nucleation layer, wherein the SiO2 layer is patterned using lithographic techniques to create an array of openings in the SiO2 layer;
- (c) transferring the substrate back into the growth chamber, and selectively growing n-type semiconductor nano-rods in the array of openings, and growing an InGaN/GaN quantum well (QW) active region on the n-type semiconductor nano-rods;
- and
- (d) growing a p-type GaN:Mg layer with a larger band gap than the QW active region on top of the QW active region, wherein, during the growth of the p-type GaN:Mg layer, deposition conditions enhance lateral growth and coalescence of the p-type GaN:Mg layer, thereby merging the nano-rods through coalescence into a continuous planar layer.
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A method of fabricating semiconductor devices, comprising:
- (a) depositing a conducting (Al,Ga)N nucleation layer on a substrate in a growth chamber, followed by a deposition of an n-type GaN:Si layer, InGaN/GaN quantum well (QW) active region, and a p-type GaN:Mg layer;
- (b) removing the substrate from a growth chamber and depositing a SiO2 layer onto the p-type GaN:Mg layer, wherein the SiO2 layer is patterned using lithographic techniques to create an array of openings in the SiO2 layer;
- (c) transferring the substrate into an etching chamber, and forming n-type semiconductor nano-rods in the array of openings;
- and
- (d) transferring the substrate into the growth chamber, and growing a p-type GaN:Mg layer on the n-type semiconductor nano-rods, wherein, during the growth of the p-type GaN:Mg layer, deposition conditions promote lateral growth and coalescence of the p-type GaN:Mg layer, thereby merging the nano-rods through coalescence into a continuous planar layer.
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Dependencies are inferred from the claim text.