Method of manufacturing a thin film transistor array panel
AssigneeSamsung Electronics Co., Ltd.
InventorTae-Young Choi
Life of this patent
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Abstract
A method for manufacturing a flexible display, includes forming a gate line including a plurality of gate electrodes with a first interval on a substrate having a coefficient of thermal expansion, sequentially depositing both a gate insulating layer covering the gate line and a semiconductor layer, etching the semiconductor layer by using a mask having a plurality of semiconductor patterns with a second interval different from the first interval to form a semiconductor, forming both a data line including a source electrode and a drain electrode on the semiconductor and the gate insulating layer, and forming a pixel electrode coupled with the drain electrode.
Claims12
A method of manufacturing a display, comprising:
- forming a gate line on a substrate, the gate line having a plurality of gate electrodes with a first interval provided between adjacent gate electrodes;
- sequentially depositing a gate insulating layer that covers the gate line and a semiconductor layer;
- forming a semiconductor by etching the semiconductor layer with a mask to form a plurality of semiconductor patterns with a second interval provided between adjacent semiconductor patterns, the second interval being different from the first interval;
- forming a data line, a source electrode, and a drain electrode and the gate insulating layer;
- and
- forming a pixel electrode coupled with the drain electrode.
A method of forming gate patterns on a substrate, comprising:
- forming a gate mask having a predetermined distance between center portions of adjacent gate electrodes to be formed on the substrate;
- depositing a gate insulating layer and a semiconductor layer on the substrate;
- and
- forming being spaced apart from each other at a distance that is equal the predetermined distance plus a distance relating to the coefficient of thermal expansion of the substrate,
- wherein the center portions of the adjacent gate electrodes correspond with the center portions of the adjacent semiconductor patterns due to the thermal expansion.
Dependencies are inferred from the claim text.